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Functional Description
5-48
82801AA and 82801AB Datasheet
NOTE:
Some wake events can be preserved through power failure.
5.12.2
System Power Planes
The system has several independent power planes, as described in
Table 5-34
. Note that when a
particular power plane is shut off, it should go to a 0V level.
s
Table 5-33. State Transition Rules for ICH
Present
State
Transition Trigger
Next State
G0/S0/C0
Processor halt instruction
Level 2 Read
SLP_EN bit set
Power Button Override
Mechanical Off/Power Failure
G0/S0/C1
G0/S0/C2
G1/Sx or G2/S5state
G2/S5
G3
G0/S0/C1
Any Enabled Break Event
STPCLK# goes active
Power Button Override
Power Failure
G0/S0/C0
G0/S0/C2
G2/S5
G3
G0/S0/C2
Any Enabled Break Event
STPCLK# goes inactive and previously
in C1
Power Button Override
Power Failure
G0/S0/C0
G0/S0/C1
G2/S5
G3
G1/S1,
G1/S3, or
G1/S4
Any Enabled Wake Event
Power Button Override
Power Failure
G0/S0/C0
G2/S5
G3
G2/S5
Any Enabled Wake Event
Power Failure
G0/S0/C0
G3
G3
Power Returns
Optional to go to S0/C0 (reboot) or G2/S5
(stay off until power button pressed). (See
Note 1)
Table 5-34. System Power Plane
Plane
Controlled
By
Description
MAIN
SLP_S3#
signal
When SLP_S3# goes active, power can be shut off to any circuit not
required to wake the system from the S3 state. Since the S3 state requires
that the memory context be preserved, power must be retained to the main
memory.
Devices on the PCI bus, LPC interface downstream Hub Interface (and AGP
for the ICH 82801AA) is, typically, shut off when the Main power plane is
shut; there may be small subsections powered.
MEMORY
SLP_S5#
signal
When the SLP_S5# goes active, power can be shut off to any circuit not
required to wake the system from the S4 or S5 state. Since the memory
context does not need to be preserved in the S5 state, the power to the
memory can also be shut down.
DEVICE[n]
GPIO
Individual subsystems may have their own power plane. For example, GPIO
signals may be used to control the power to disk drives, audio amplifiers, or
the display screen.