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82801AA and 82801AB Datasheet
8-9
LPC Interface Bridge Registers (D31:F0)
8.1.16
PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control
(LPC I/F—D31:F0)
Offset Address:
PIRQA
–
60h, PIRQB
–
61h,
PIRQC
–
62h, PIRQD
–
63h
80h
No
Attribute:
R/W
Default Value:
Lockable:
Size:
Power Well:
8 bits
Core
8.1.17
SERIRQ_CNTL—Serial IRQ Control (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
64h
10h
No
Attribute:
Size:
Power Well:
R/W
8 bits
Core
Bit
Description
7
Interrupt Routing Enable (IRQEN).
0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified in bits[3:0].
1 = The PIRQ is not routed to the 8259.
Note: If the PIRQ is intended to cause an interrupt to the ICH’s integrated I/O APIC, then this bit
should be set to 0 and the APIC_EN bit should be set to 1. The IRQEN must be set to 0 and
the PIRQ routed to an 8259 interrupt via the IRQ Routing filed (bits[3:0). The corresponding
8259 interrupt must be masked via the appropriated bit in the 8259’s OCW1 (Interrupt Mask)
register. The IOAPIC must then be enabled by setting the APIC_EN bit in the GEN_CNTL
register.
6:4
Reserved.
3:0
IRQ Routing.
(ISA compatible).
0000 = Reserved
0001 = Reserved
0010 = Reserved
0011 = IRQ3
0100 = IRQ4
0101 = IRQ5
0110 = IRQ6
0111 = IRQ7
1000 = Reserved
1001 = IRQ9
1010 = IRQ10
1011 = IRQ11
1100 = IRQ12
1101 = Reserved
1110 = IRQ14
1111 = IRQ15
Bit
Description
7
Serial IRQ Enable (SIRQEN).
1 = Serial IRQs are recognized. The SERIRQ pin is configured as SERIRQ.
0 = The buffer is input only and internally SERIRQ will be a ‘1’.
6
Serial IRQ Mode Select (SIRQMD).
For systems using Quiet Mode, this bit should be set to 1
(Continuous Mode) for at least one frame after coming out of reset before switching back to Quiet
Mode. Failure to do so will result in the ICH not recognizing SERIRQ interrupts.
1 = The serial IRQ machine will be in continuous mode.
0 = The serial IRQ machine will be in quiet mode.
5:2
Serial IRQ Frame Size (SIRQSZ).
Fixed field that indicates the size of the SERIRQ frame. In the
ICH, this field needs to be programmed to 21 frames (0100). This is an offset from a base of 17
which is the smallest data frame size.
1:0
Start Frame Pulse Width (SFPW).
This is the number of PCI clocks that the SERIRQ pin will be
driven low by the serial IRQ machine to signal a start frame. In continuous mode, the ICH will drive
the start frame for the number of clocks specified. In quiet mode, the ICH will drive the start frame for
the number of clocks specified minus one, as the first clock was driven by the peripheral.
00 = 4 clocks
01 = 6 clocks
10 = 8 clocks
11 = Reserved