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Functional Description
5-62
82801AA and 82801AB Datasheet
If there is activity, various bits in the DEVACT_STS register are set to a 1. Software clears the bits
to 0 by writing a 1 to the bit position.
The DEVACT_STS register allows for monitoring various internal devices, or Super I/O devices
(SP, PP, FDC) on LPC or PCI, keyboard controller accesses, or audio functions on LPC or PCI.
Other PCI activity can be monitored by checking the PCI interrupts.
5.13
System Management (D31:F0)
5.13.1
Overview of System Management Functions
The ICH provides various functions to make a system easier to manage and to lower the Total Cost
of Ownership (TCO) of the system. Features and functions can be augmented via external A/D
converters and GPIO, as well as an external microcontroller.
The following features and functions are supported by the ICH:
Processor present detection.
— Detects if the processor fails to fetch the first instruction after reset.
Various Error detection, reported by the host controller
— Can generate SMI#, SCI, SERR, NMI, or TCO interrupt
Intruder Detect input
— Can generate TCO interrupt or SMI# when the system cover is removed.
Alert On LAN (ICH: 82801AA only)
Note:
Voltage ID from the processor can be read via GPI signals.
5.13.2
Theory of Operation
The System Management functions are designed to allow the system to diagnose failing
subsystems. The intent of this logic is that some of the system management functionality will be
provided without the aid of an external microcontroller.
Detecting a System Lockup
When the processor is reset, it is expected to fetch its first instruction. If the processor fails to fetch
the first instruction after reset, the TCO timer times out twice and the ICH asserts PCIRST#.
Handling an Intruder
The ICH’s INTRUDER# input signal can be attached to a switch that is activated by the system’s
case being open. This input has a 2 RTC clock debounce. If INTRUDER# goes active (after the
debouncer), this sets the INTRD_DET bit in the TCO2_STS register. The INTRD_SEL bits in the
TCO2_CNT register can enable the ICH to cause an SMI# or interrupt. The BIOS or interrupt
handler can then cause a transition to the S5 state by writing to the SLP_EN bit.
— Sends hardcoded SMBus message over ALERTCLK and ALERTDATA pins to LAN
controller.