參數(shù)資料
型號(hào)： P32P4911A
廠商： NXP SEMICONDUCTORS
元件分類： 光電元器件
英文描述： PRML Read Channel with PR4, 8/9 ENDEC, FWR Servo
中文描述： 1 CHANNEL READ CHANNEL, PQFP100
封裝： 14 X 14 X 1.40 MM, PLASTIC, LQFP-100
文件頁(yè)數(shù)： 11/63頁(yè)
文件大?。?/td> 257K
代理商： P32P4911A
1996 Jul 25
11
Philips Semiconductors
Product specification
PRML Read Channel with PR4,
8/9 ENDEC, FWR Servo
P32P4911A
Pulse Qualification Circuit Descriptions
This device utilizes three different types of pulse qualification, one exclusively for servo reads, one primarily for servo
reads, and the other for data reads.
S
ERVO
R
EAD
M
ODE
For servo gray code reads, either a dual level (window type) qualifier or a hysteresis type level qualifier may be selected.
If the PDM bit in the Servo Filter Cutoff Register is set to 0, then the window qualifier is selected, and if the PDM bit is a
1, the hysteresis qualifier is selected. The polarity of the RDS/RDS is selected by the SMS bit (Servo Mode Select) in
the Data Rate Register. If SMS=0 then RDS is active-Low and if SMS=1 then RDS is active-High.
D
UAL
L
EVEL
(W
INDOW
) Q
UALIFIER
During servo reads (SG High) a dual level type of pulse qualifier is used. The level qualification thresholds are set by a
6-bit DAC which is controlled by the Servo Level Threshold Register (LDS). The register value is relative to the peak
voltage at the output of the continuous time filter, derived off of the same reference voltage internal to the chip. The
positive and negative thresholds are equal in magnitude. The state of the adaptive threshold level enable (ALE) bit in
the WP/LT Register does not affect this DAC's reference. The RDS/RDS and the PPOL outputs of the level qualifier
indicate a qualified servo pulse and the polarity of the pulse, respectively. The RDS/RDS and PPOL outputs are only
active when the SG input is High.
H
YSTERESIS
Q
UALIFIER
The hysteresis qualifier performs the same as the window qualifier except that the hysteresis qualifier guarantees that
the second of two consecutive pulses of the same polarity will not be qualified. The hysteresis qualifier will only qualify
pulses of alternating polarity.
D
ATA
R
EAD
M
ODE
In data read mode (RG High), the dual level qualifier used for servo reads, is used during VCO sync field counting. Its
qualification thresholds are set by a 6-bit DAC which is controlled by the Data Level Threshold Register (LD). The
register value is relative to the peak voltage at output of the continuous time filter and the DAC both referenced to band
gap voltage. The positive and negative thresholds are equal in magnitude. The state of the adaptive threshold level
enable (ALE) bit in the WP/LT Register does not affect the DAC's reference until the sync field count has been achieved.
The RDS/RDS and the PPOL outputs of the level qualifier are not active in data read mode.
V
ITERBI
Q
UALIFIER
The second type of pulse qualification, the Viterbi qualifier, is only used during data read mode after the sync field count
has been achieved. The Viterbi qualifier has two significant blocks, one that feeds the other. The first block is the
sampled pulse detector and the second is the survival sequence register.
The sampled pulse detector performs the pulse acquisition/detection in the sampled domain. It acquires pulses by
comparing the code clock sampled analog waveform to the positive and negative thresholds established by the
programmable Viterbi threshold window. The threshold window is defined to be the difference between the positive and
negative threshold levels. The threshold window, Vth, is set by a 7-bit DAC which is controlled by the Viterbi Detector
Threshold Register (VDT). While the window size is fixed by the programmed Vth value, the actual positive and negative
thresholds track the most positive and the most negative samples of the equalized input signal. For example, the Viterbi
positive signal threshold, Vpt = Vpeak (+) max if the previous detected level was (+). If the previous detect level was (-),
Vpt = Vpeak(-)max + Vth, where Vpeak(-)max is the maximum amplitude of the previously detected negative signal.
Normally Vth is set to equal Vpeak (approx. 500 mV).
After the pulses have been detected they must be further qualified by the survival sequence registers and associated
logic. This logic guarantees that for sequential pulses of the same polarity within the maximum run length, only the latest
is qualified. In this way, only the pulse of greatest amplitude will be qualified.
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