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參數(shù)資料
| 型號： | P32P4911A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 光電元器件 |
| 英文描述： | PRML Read Channel with PR4, 8/9 ENDEC, FWR Servo |
| 中文描述： | 1 CHANNEL READ CHANNEL, PQFP100 |
| 封裝： | 14 X 14 X 1.40 MM, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 35/63頁 |
| 文件大?。?/td> | 257K |
| 代理商： | P32P4911A |
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1996 Jul 25
35
Philips Semiconductors
Product specification
PRML Read Channel with PR4,
8/9 ENDEC, FWR Servo
P32P4911A
Serial Port Register Definitions (Continued)
Complete Register ID String
A3
A2
A1
A0
S2
S1
S0
R/W
Control Test Mode Register
(CT)
1
Bit 7
0
EFR
0
Sample clock source
0 = sample clock is from the DS VCO, normal operation
1 = sample clock is from the TBG output, a test mode
Factory reserved bit, must be set to 0 in application (enables
charge pump)
Multiplexed test point selection
0
0
1
0
0
84H
Bit 6
ECP
Bits 5-3
TP3-1
TP3
TP2
TP1
Function
TPA+, TPA-
TPB+, TPB-
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Test Points Off
Survival Out/In
Eq Cont/Phase Det
Viterbi Survival In
Equalizer Outputs
EQ out/Survival In
EQ out/Survival Out
EQ out/VCO/2
EQ out/TBG out
1
Bit 2
high impedance
SSOUT A, B (sngl)
Equalizer Control (diff)
SSIN B+,B- (sngl)
Equalizer A (diff)
Equalizer A (diff)
Equalizer A, B (sngl)
Equalizer A, B (sngl)
Equalizer A, B (sngl)
0
Enable double RCLK drive (TME = X)
0 = RCLK drive at 1x in byte wide mode, 2x in nibble mode
1 = RCLK drive at 2x in both byte wide and nibble mode
Enable VRDT input (TME=1)
0 = Viterbi survival outputs to the data decoder, normal use
1 = Digital input to the data decoder, fixed AGC filter gain =
24dB used in testing only.
Enable TBG pump down
0 = not in pump down test mode
1 = continuous pump down, for test only
Training Termination (TME = 0)
0 = termination training when SBD goes Low
1 = terminate training 4 bytes after framing
Enable TBG pump up (TME = 1)
0 = not in pump up test mode
1 = continuous pump up, for test use only
FLTR1+ sources current; FLTR1- sinks current
high impedance
SSIN A+, A- (sngl),
Phase Detect Out (diff),
SSIN A+, A- (sngl),
Equalizer B (diff)
SSIN A+, A- (sngl)
SSOUT A, B (sngl)
DS VCO/2 (diff) for RG = 1
TBG out (diff) for RG = 0
0
0
Control Test Mode Register
(CT)
0
RCK2X/
VRDT
0
0
1
84H
Bit 1
DT
Bit 0
FSB/UT
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