參數(shù)資料
型號: P32P4911A
廠商: NXP SEMICONDUCTORS
元件分類: 光電元器件
英文描述: PRML Read Channel with PR4, 8/9 ENDEC, FWR Servo
中文描述: 1 CHANNEL READ CHANNEL, PQFP100
封裝: 14 X 14 X 1.40 MM, PLASTIC, LQFP-100
文件頁數(shù): 42/63頁
文件大小: 257K
代理商: P32P4911A
1996 Jul 25
42
Philips Semiconductors
Product specification
PRML Read Channel with PR4,
8/9 ENDEC, FWR Servo
P32P4911A
Analog Output Pins (Continued)
Pin Name
Type
Pin Function
ATO
O
ANALOG TEST OUT: This test point output provides a monitor of one of three signals.
They are the equalizer quality signal, the amplitude asymmetry signal, and the DAC
outputs. The selected output is determined by the programming of the ATOSEL bits in
the Power Down Register. If the DAC outputs are selected, the last DAC written to by the
serial control register is the DAC monitored. Signal at ATO is referenced to MAXREF/2.
SERVO OUTPUT: This signal is a full-wave-rectified version of the differential signal at
DP/DN. It is referenced to the SREF output voltage. Open emitter output which requires
an external pull down current when SDIEN is high. When SDIEN is low, a 360
μ
A pull
down current is interally provided.
SERVO REFERENCE OUTPUT: Reference voltage for the SEROUT signal. It is set to
one Vbe below the VRC voltage. This is an open emitter output which requires an
external pull down current when SDIEN is high. When SDIEN is low, a 360
μ
A pull down
current is interally provided.
ATO REFERENCE OUTPUT: +3.2V DC reference voltage which can be used as a
baseline for the ATO test point. Can be used for the reference for an external A/D
converter.
AGC REFERENCE OUTPUT: Allows programmable fixed gain operation when connected
to either or both of the BYPD or BYPS pins.
SEROUT
O
SREF
O
MAXREF
AGCREF
Analog Control Pins
Pin Name
Type
Pin Function
BYP
-
The data AGC integrating capacitor, C
, is connected between BYP and VPA. This pin
is used when not in servo read mode (SG = 0).
The servo AGC integrating capacitor, C
, is connected between BYPS and VPA. This
pin is used when in servo read mode (SG = 1).
TBG PLL LOOP FILTER: Differential connection points for the time base generator PLL
loop filter components.
DS PLL LOOP FILTER: Differential connection points for the data separator PLL loop
filter capacitor.
CURRENT REFERENCE RESISTOR INPUT: An external 1%, 10 k
(for max data rate
of 125 Mbit/s) or 12.1 k
(for max data rate of 100 Mbit/s) resistor is connected from this
pin to ground to establish a precise internal reference current for the data separator and
the time base generator DACs.
FILTER REFERENCE RESISTOR INPUT: An external 1%, 12.1 k
resistor is connected
from this pin to ground to establish a precise PTAT (proportional to absolute temperature)
reference current for the filter DACs.
AGC REFERENCE VOLTAGE: VRC is derived by a bandgap reference from VPA.
LOWZ ONE-SHOT ADJUST: The resistor connected between this pin and GND
determines the length of the lowz period. t
LZ
= (R
LZ
+ 0.5) * 0.1
μ
s/k
.
FAST RECOVERY ONE-SHOT ADJUST: The resistor connected between this pin and
GND determines the length of the fast decay period. t
FR
= (R
FR
+ 0.5) * 0.1
μ
s/k
.
ULTRA FAST DECAY CURRENT ADJUST: The resistor connected between this pin and
VPA determines the ultra fast decay current given by the equation I = (VPA - VBYP)/Rufd.
This pin may be left open if ultra fast decay action is not required.
BYPS
-
FLTR1+,
FLTR1-
FLTR2+,
FLTR2-
RR
-
-
-
VRX
-
VRC
WRDEL
-
-
AGCDEL
-
AGCRST
-
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