參數(shù)資料
型號(hào)： P32P4911A
廠商： NXP SEMICONDUCTORS
元件分類： 光電元器件
英文描述： PRML Read Channel with PR4, 8/9 ENDEC, FWR Servo
中文描述： 1 CHANNEL READ CHANNEL, PQFP100
封裝： 14 X 14 X 1.40 MM, PLASTIC, LQFP-100
文件頁(yè)數(shù)： 29/63頁(yè)
文件大小： 257K
代理商： P32P4911A
1996 Jul 25
29
Philips Semiconductors
Product specification
PRML Read Channel with PR4,
8/9 ENDEC, FWR Servo
P32P4911A
generator output, but when the Read Gate input (RG) goes High, the PLL's reference input is switched to the filtered
incoming read signal.
A
CQUISITION OF
DS VCO S
YNC
When the Read Gate input is asserted, the read sequence is initiated. At this time an internal counter begins counting
the pulses that are qualified by the dual level pulse qualifier given the polarity changes of the incoming 1,1,-1,-1,1,1 read
back pattern defined by the VCO sync field. When the count reaches 4, the internal read gate is asserted and the DS
PLL input is switched from the TBG's VCO output to the sampled data input. This is also the point at which the DS PLL's
phase detector is switched from the phase-frequency detector to the decision directed phase detector. The counter is
also used to determine whether the selected sync field count, SFC, has been achieved. When the counter reaches the
value specified by SFC, the data synchronizer PLL is assumed to be locked and settled (VCO lock). Also at SFC, the
phase detector gain switch and the AGC mode switch occur. To allow for different preamble lengths, the SFC can be set
to 64, 80, 96 or 128 from the Sample Loop Control Register. These values for the SFC may be thought of as the number
of code clock periods in the sync field, but they actually represent twice the number of incoming polarity changes
required.
VCO L
OCK
, PD G
AIN
, AGC M
ODE
S
WITCH
,
AND
C
ODE
W
ORD
B
OUNDARY
D
ETECTOR
E
NABLE
At SFC, one of two phase tracking methods will be chosen depending on the Enable Phase Detector Gain Switching
(GS) bit in the Control Operating Mode Register. When the GS bit is High, the phase detector gain is reduced by a factor
of 6 or 10 as dictated by the GS_10 bit after the SFC count is reached. When the GS bit is Low, no phase detector gain
switching takes place.
Also after SFC, the AGC feedback will be switched from the continuous time fullwave rectifier to sampled data feedback.
At SFC, the internal VCO lock signal activates the code word boundary detection circuitry to define the proper decode
boundaries. Also, at count SFC, the RCLK generator source switches from the TBG's VCO output to the DS VCO clock
signal which is phase locked to the incoming read data samples. The DS VCO is assumed locked to the incoming read
samples at this point. At SFC a maximum of 1 RCLK time period may occur for the RCLK transition, however, no short
duration glitches will occur. After the code word detection circuitry finds the proper code word boundary, the RCLK
generator is again resynchronized to guarantee that the RCLK is in sync with the data. The RCLK output will not glitch
and will not toggle during this RCLK generator resynchronization for up to 2 byte times maximum.
Also at the code word boundary detect, the internal 9-bit code words are allowed to pass to the ENDEC for decoding.
This decoding will occur until read gate is deasserted.
Figure 17: Read Sequence - Dual Sync Byte Modes
GAP
8 BYTES MIN.
5 BYTES MIN.
1 BYTE
NRZ DATA
HIGH Z
00H
00H
00H
USER DATA
RG
SBD
1 BYTE
69H
1 BYTE
00H
SYNC
BYTE#2
SYNC
BYTE#1
TRAIN
BYTE
TRAINING
SEQUENCE
VCO SYNC
FIELD
SCRAMBLED AND ENCODED
USER DATA
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