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參數(shù)資料
| 型號： | P32P4911A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 光電元器件 |
| 英文描述： | PRML Read Channel with PR4, 8/9 ENDEC, FWR Servo |
| 中文描述： | 1 CHANNEL READ CHANNEL, PQFP100 |
| 封裝： | 14 X 14 X 1.40 MM, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 5/63頁 |
| 文件大?。?/td> | 257K |
| 代理商： | P32P4911A |
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1996 Jul 25
5
Philips Semiconductors
Product specification
PRML Read Channel with PR4,
8/9 ENDEC, FWR Servo
P32P4911A
Time Base Generator:
Less than 1% frequency resolution
Up to 141 MHz frequency output
Independent M and N divide-by registers
No active external components required
Data Separator:
Fully integrated data separator includes data synchronizer and 8,9 GCR ENDEC
Register programmable to 125 Mbit/s operation
Fast Acquisition, sampled data phase lock loop
Decision directed clock recovery from data samples
Adaptive clock recovery thresholds
Programmable damping ratio for data synchronizer PLL is constant for all data rates
Data scrambler/descrambler to reduce fixed pattern effects
4-bit nibble and byte-wide NRZ data interfaces
Nibble clock is available during byte-wide mode
Time base tracking, programmable write precompensation
Differential PECL write data output
Integrated sync byte detection, single byte or dual ("or" type)
Semi-auto training and sync byte generation available for single sync byte operation
Surface defect scan mode
Servo:
Wide bandwidth, precision full-wave rectifier
Separate, automatically selected, registers for servo c, boost, and threshold
SEROUT and SREF pins to provide a differential full-wave rectified servo signal
SELVRC and SDIEN control pins for dc gain and offset calibration
AGCREF output to provide 2-bit DAC-controlled voltage for applications requiring a fixed gain in servo mode
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