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參數(shù)資料
| 型號： | P32P4911A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 光電元器件 |
| 英文描述： | PRML Read Channel with PR4, 8/9 ENDEC, FWR Servo |
| 中文描述： | 1 CHANNEL READ CHANNEL, PQFP100 |
| 封裝： | 14 X 14 X 1.40 MM, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 24/63頁 |
| 文件大?。?/td> | 257K |
| 代理商： | P32P4911A |
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1996 Jul 25
24
Philips Semiconductors
Product specification
PRML Read Channel with PR4,
8/9 ENDEC, FWR Servo
P32P4911A
W
RITE
P
RECOMPENSATION
The write precompensation circuitry is provided to compensate for media bit shift caused by magnetic nonlinearities. The
circuit recognizes specific write data patterns and can add delays in the time position of write data bits to counteract the
magnetic nonlinearity effect. The magnitude of the time shift, WPC, is programmable via the Write Precomp Register
and is made proportional to the time base generator's VCO period (i.e., data rate). The circuit performs write
precompensation only on the second of two consecutive "ones" and only shifts in the late direction. If more than two
consecutive "ones" are written, all but the first are precompensated in the late direction.
Servo Demodulator Circuit Description
Servo functionality is provided by two separate circuits: the servo full-wave rectifier circuit, and the previously described
dual level pulse qualifier circuit. To support embedded servo applications, P32P4911A provides separate programmable
registers for servo mode filter cutoff frequency, boost, and qualification threshold. The values programmed in these
registers are selected upon entry into servo mode (SG=1). The RDS pulse polarity is programmable via the Servo Mode
Select (SMS) bit in the Data Rate Register. This bit also determines the polarity of the RDS/RDS output. In addition, the
RDS/RDS pulse width is also programmable via the RDSPW bit in the sample Loop Control Register (SLC).
The servo demodulator circuit outputs a full wave rectified version of the signal at DP/DN to the SEROUT pin when SG=1.
The signal is referenced to the SREF output pin which is biased at about 3.1V below VPA. The SEROUT signal has a
gain of 0.6 V/Vppd so that a 1.4V signal at DP/DN will produce a 0.84V peak excursion at SEROUT. When SG=0, the
SEROUT pin outputs either SREF or SREF + 200 mV. The SELVRC input pin selects which DC voltage is output in this
mode. The 200 mV offset can be used to calibrate the gain of the A/D converter which is driven by the SEROUT signal.
Servo Timing Outputs
The dual level qualifier that was previously described is used to generate the RDS/RDS and PPOL timing signals. The
RDS/RDS output pin pulses Low for each positive or negative servo peak that is qualified by the dual level qualifier. The
pulse width of RDS/RDS may be selected as either 15 ns or 27 ns with the RDSPW bit in the Sample Loop Control
Register. The PPOL output pin provides the pulse polarity information for the qualified peaks, where PPOL=1 for a
positive peak and PPOL=0 for a negative peak. To reduce noise propagation, the RDS/RDS and PPOL outputs are only
active in servo mode.
Serial Port Circuit Description
The serial port interface is used to program the P32P4911A's seventeen internal registers. The serial port is enabled for
data transfer when the Serial Data Enable (SDEN) pin is High ("1"). SDEN must be asserted High prior to any
Figure 13: RDS/RDS and PPOL vs. DP/DN Relationship
DP/DN
+ Threshold
(+LSth)
- Threshold
RDS
PPOL
(-LSth)
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