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參數(shù)資料
| 型號： | P32P4911A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 光電元器件 |
| 英文描述： | PRML Read Channel with PR4, 8/9 ENDEC, FWR Servo |
| 中文描述： | 1 CHANNEL READ CHANNEL, PQFP100 |
| 封裝： | 14 X 14 X 1.40 MM, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 38/63頁 |
| 文件大小： | 257K |
| 代理商： | P32P4911A |
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1996 Jul 25
38
Philips Semiconductors
Product specification
PRML Read Channel with PR4,
8/9 ENDEC, FWR Servo
P32P4911A
Serial Port Register Definitions (Continued)
Complete Register ID String
A3
A2
A1
A0
S2
S1
S0
R/W
Control Operating Register
(CM1)
1
1
0
1
0
1
0
0
D4H
Bit 7
AUTOTR
Enables Semi-Automatic training and sync byte generation
0 = disabled (normal operation)
1 = enabled (single sync byte only)
Selects AGC control mode
0 = Direct mode i.e., external control signals must be
provided
1 = Timed mode i.e., control provided by one shot timing
from SG and WG/WG
Write gate polarity
0 = active High, (normal operation)
1 = active Low
Enable Nibble interface
0 = Nibble interface disabled, i.e., byte-wide interface
enabled
1 = Nibble (NRZ3-0) interface enabled
Bypass Time Base Generator
0 = data synchronizer reference frequency is TBG output,
(normal operation)
1 = data synchronizer reference frequency is FREF input
Disable Data Scrambler/Descrambler
0 = enabled, (normal operation)
1 = disabled
DS Phase Detector gain switching
0 = enabled, (normal operation)
1 = disabled
Enable Direct Write From Byte-wide NRZ (Bypasses
scrambler and ENDEC)
0 = disabled; (normal operation)
1 = enabled,
Bit 6
AGCSEL
Bit 5
WGP
Bit 4
NIB
Bit 3
BT
Bit 2
SD
Bit 1
GS
Bit 0
DW
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