參數(shù)資料
型號(hào)： P32P4911A
廠商： NXP SEMICONDUCTORS
元件分類： 光電元器件
英文描述： PRML Read Channel with PR4, 8/9 ENDEC, FWR Servo
中文描述： 1 CHANNEL READ CHANNEL, PQFP100
封裝： 14 X 14 X 1.40 MM, PLASTIC, LQFP-100
文件頁(yè)數(shù)： 27/63頁(yè)
文件大?。?/td> 257K
代理商： P32P4911A
1996 Jul 25
27
Philips Semiconductors
Product specification
PRML Read Channel with PR4,
8/9 ENDEC, FWR Servo
P32P4911A
The P32P4911A also allows the precoder to be preset when the first training byte arrives at the precoder. With Control
Operating Mode Register #2 bit 3 (TME) and bit 0 (PCSDIS) set to 0, the P32P4911A allows presetting of the precoder.
Bit 2 (PCSPOL) of the Control Operating Mode Register #2 allows the precoder to be preset if PFSPOL is set to 1 and
reset if set to 0.
T
RAINING AND
S
YNC
B
YTE
G
ENERATION
The P32P4911A supports two modes of sync byte detection, single byte and dual "or" byte, and two modes of training
and sync byte generation, manual and semi-automatic. The manual mode is generally recommended because it can be
used for either dual or single sync byte detection and provides more flexibility in altering the number of training bytes to
be written. The semi-automatic mode can only be used to generate an internally fixed number of training bytes and a
single sync byte, but saves controller state machine space.
M
ANUAL
M
ODE
In the manual mode, the device will continue to autogenerate the sync field pattern until a 93H is latched at the NRZ
interface, and detected. The device encodes the 93H pattern and writes the result as the training pattern.
For the single sync byte detection mode, a recommended minimum of 5 bytes of 93H must be written to the NRZ interface
to write the 5 byte equalizer training pattern. Next, the NRZ data must be changed to 69H for 1 byte time to write the
single sync byte.
For the dual sync byte detection mode, a recommended minimum of 4 bytes of 93H must be written to the NRZ interface
to write the minimum 4 byte equalizer training pattern. The NRZ data must then be changed to 1FH for one byte time to
write the first sync byte. The NRZ data must then be changed to 93H for one byte time to write a training/propagation
byte. Next, the NRZ data must be changed to 69H for one byte time to write the second sync byte.
S
EMI
-A
UTOMATIC
M
ODE
In the semi-automatic mode, the device will continue to autogenerate the sync field pattern until a FFH is latched at the
NRZ interface, and detected. The device then internally generates the encoded the 93H pattern for 5 byte times and
writes the result as the training pattern. It then internally generates the encoded 69H pattern for 1 byte time to write the
single sync byte. To maintain proper controller synchronization, the FFH should be presented at the NRZ interface for
Figure 15: Hard Sector Write Sequence - Dual Sync
GAP
8 BYTES MIN.
4 BYTES MIN.
1 BYTE
NRZ DATA (WRITE)
00H
93H
69H
USER DATA
WG
1 BYTE
1FH
1 BYTE
93H
VCO SYNC
FIELD
TRAINING
SEQUENCE
SYNC
BYTE#1
TRAIN
BYTE
SYNC
BYTE#2
SCRAMBLED AND ENCODED
USER DATA
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