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參數(shù)資料
| 型號： | P32P4911A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 光電元器件 |
| 英文描述： | PRML Read Channel with PR4, 8/9 ENDEC, FWR Servo |
| 中文描述： | 1 CHANNEL READ CHANNEL, PQFP100 |
| 封裝： | 14 X 14 X 1.40 MM, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 18/63頁 |
| 文件大?。?/td> | 257K |
| 代理商： | P32P4911A |
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1996 Jul 25
18
Philips Semiconductors
Product specification
PRML Read Channel with PR4,
8/9 ENDEC, FWR Servo
P32P4911A
Amplitude Asymmetry Detection and Correction
In the presence of amplitude asymmetry, such as that generated by MR heads, the sampled data processor (SDP) will
be presented with zeros generated in one of two ways. The first is due the lack of a magnetic transition and will be
referred to as a "real" zero. The second is produced by the superposition of adjacent +1 and -1 magnetic transitions and
results in zero samples that shall be referred to as "cancelled" zeros. In the presence of amplitude asymmetry from an
MR head, the "real" zeros are zero, but the "cancelled" zeros are offset by the difference between the +1 and -1 samples.
The offset correction circuit forces the ground reference of the sampled data processor to the center of the "real" and
"cancelled" zero sample levels.
The integration time constant is increased by a factor of 4 to 1.0
μ
s, after the sync byte has been detected.
A
MPLITUDE
A
SYMMETRY
M
ONITOR
P
OINT
An amplitude asymmetry quality factor "Qasym" may be selected to be output on the ATO output pin by programming
the ASEL bits in the Power Down Register. This signal is derived by computing the average distance of the "real" and
"canceled" zeros from the sampled data processor's system ground which was established between the two zeros levels
by the offset correction circuit. The average distance is a measure of the asymmetry present in the MR read back signal.
A gain of 4 from the sampled values is utilized and is low pass filtered with a time constant that is programmable to one
of four different values by programming the two QTC bits in the Control Operating Mode Register #2.
The signal is then buffered and differentially multiplexed to the ATO pin. The signal is referenced to MAXREF/2.
The asymmetry quality factor can be held at the value present at sync byte detect by setting the FREZQ bit in the WP/LT
Register. The value will be held for 10 ms and is NOT reset. The ATO output may also be externally filtered to provide
time constants that are appropriate for averaging over major portions of, or an entire sector. The capacitors on externally
added filters must be externally reset. Note that any external filtering added to ATO output pin will affect both the
amplitude asymmetry monitor signal and the equalization quality monitor signal since they are both muxed to the ATO
output pin.
Adaptive Equalizer Circuit Description
Up to 7 dB of equalization for fine shaping of the incoming read signal to the PR4 waveshape is provided by a 5 tap,
sampled analog, transversal filter. This filter provides a self adaptive multiplier coefficient for the inner taps and a
programmable coefficient for the outer taps. Both inner taps use the same coefficient (km
1
), and both outer taps use the
same coefficient (km
2
).
For the adaptive inner taps, the value of km
1
is adjusted to force "zero" samples to zero volts. A special equalizer training
pattern, located after the VCO sync field in the sector format, is used to provide an optimum signal for the equalizer to
adapt to. The adaptive property of these taps is enabled or disabled by the AEE bit in the Sample Loop Register. If the
adaptive property is enabled, whether adaptation occurs only during the training pattern or both during the training
pattern and the user data is controlled by the AED bit in the Sample Loop Register.
The adaptation can be observed when the equalizer control voltage is selected as the TPA+/TPA- output. The equalizer
control voltage is approximately related to km1 by:
km1 = 0.009 * Date Rate (Mbit/s) * (TPA+ - TPA-)
The multiplier coefficients for the adaptive taps can be held for up to 10 ms if the EQHOLD input is brought High after
sync byte detect has occurred during a previous read in which proper training has occurred. The EQHOLD input pin may
be asserted at any time during a read cycle and the adaptive coefficient Km1 present at that time will be held, provided
no leakage occurs, until the EQHOLD input is de-asserted.
The multiplier coefficient, km
2,
for the outer taps is programmable between +0.117 and -0.135 by the 4 km bits (bits 4-7)
in the Control Operating Mode Register #2
.
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