參數(shù)資料
型號(hào)： P32P4911A
廠商： NXP SEMICONDUCTORS
元件分類： 光電元器件
英文描述： PRML Read Channel with PR4, 8/9 ENDEC, FWR Servo
中文描述： 1 CHANNEL READ CHANNEL, PQFP100
封裝： 14 X 14 X 1.40 MM, PLASTIC, LQFP-100
文件頁(yè)數(shù)： 21/63頁(yè)
文件大?。?/td> 257K
代理商： P32P4911A
1996 Jul 25
21
Philips Semiconductors
Product specification
PRML Read Channel with PR4,
8/9 ENDEC, FWR Servo
P32P4911A
In the read mode the decision-directed timing recovery updates the PLL by comparing amplitudes of adjacent "one"
samples or comparing the "zero" sample magnitude to ground for the entire sample period. A special (non IBM) algorithm
is used to prevent "hang up" during the acquisition phase. The determination of whether a sample is a "one" or a "zero"
is performed by a dedicated, dual mode, threshold comparator. This comparator's threshold levels are determined by
the value, Lth, programmed in the Data Threshold Register. The fixed level threshold before the sync field count (SFC)
has been achieved will be 1.4 times the threshold level after SFC since this is the ratio of the peak signal to the sampled
"1" signal amplitude for PR4. The dual mode nature of this comparator allows the selection of either symmetric fixed or
independent self adapting (+) and (-) thresholds by programming the adaptive level enable (ALE) bit in the WP/LT
Register. Also at SFC, the gain of the phase detector is reduced by a factor of 6 or 10, selectable by the GS bit in the
Damping Ratio Control register. This gain shift increases the loop's noise immunity during data tracking by reducing its
bandwidth.
The adaptive reference allows the specification of the threshold value to be a percentage of an averaged peak value.
When adaptive mode is selected, the fixed thresholds are used until the sync field count (SFC) has been reached, then
the adaptive levels are internally enabled. The time constant of a single pole filter that controls the rate of adaptation, is
programmable by bits TC2-1 in the WP/LT Register.
In the write and idle modes the non-harmonic phase-frequency detector is continuously enabled, thus maintaining both
phase and frequency lock to the time base generator's VCO output signal, F
TBG
. The polarity and width of the detector's
output current pulses correspond to the direction and magnitude of the phase error.
The two phase detectors' outputs are muxed into a single differential charge pump which drives the loop filter directly.
The loop filter requires an external capacitor. The loop damping ratio is programmed by bits 6-0 in the Damping Ratio
Control Register. The programmed damping ratio is independent of data rate.
In write mode, the TBG output is used to clock the encoder, precoder, and write precompensation circuits. The output
of the precompensation circuit is then fed to the write data flip-flop which generates the write data (WD, WD) outputs.
ENDEC
The ENDEC implements an 8,9 (0,4,4) Group Coded Recording (GCR) algorithm. The code has a minimum of no zeros
between ones and a maximum of four zeros between ones for the interleaved samples. During write operations the
encoder portion of the ENDEC converts 8-bit parallel, scrambled or nonscrambled, data to 9-bit parallel code words that
are then converted to serial format. In data read operation, after the code word boundary has been detected in the Viterbi
qualified serial data stream, the data is converted to 9-bit parallel form and the decoder portion of the ENDEC converts
the 9-bit code words to 8-bit NRZ format.
S
YNC
B
YTE
D
ETECTION
The P32P4911A supports two types of sync byte detection, dual byte and single byte.
D
UAL
S
YNC
B
YTE
D
ETECTION
The P32P4911A implements a dual "or" type sync byte detection scheme to reduce the probability that a single bit error
will lead to the inability to synchronize. The two sync bytes are different and are spaced apart by one byte. The first sync
byte is 1FH and the second is 69H. Sync byte detection is considered to have occurred if either of the two sync bytes is
found but the sync byte detect output pin (SBD) is transitioned at the position in time when the second sync byte (69)
would have been detected. The data placed on the NRZ outputs when SBD goes Low is always the second sync byte
(69) regardless of which of the two was actually detected.
S
INGLE
S
YNC
B
YTE
D
ETECTION
Since the P32P4911A looks for either of the two sync bytes, the absence of the first sync byte is not an error. This allows
for only a single byte to be written and still be able to achieve synchronization. It is recommended that only the 69H be
written if single sync byte detection is desired so that when detection occurs, the data output on the NRZ pins at sync
byte detect will match the sync byte written.
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