參數(shù)資料
型號(hào)： P32P4911A
廠商： NXP SEMICONDUCTORS
元件分類： 光電元器件
英文描述： PRML Read Channel with PR4, 8/9 ENDEC, FWR Servo
中文描述： 1 CHANNEL READ CHANNEL, PQFP100
封裝： 14 X 14 X 1.40 MM, PLASTIC, LQFP-100
文件頁(yè)數(shù)： 30/63頁(yè)
文件大?。?/td> 257K
代理商： P32P4911A
1996 Jul 25
30
Philips Semiconductors
Product specification
PRML Read Channel with PR4,
8/9 ENDEC, FWR Servo
P32P4911A
A
DAPTIVE
E
QUALIZER
T
RAINING
S
EQUENCE
T
RAINING
S
EQUENCE FOR
S
INGLE
S
YNC
B
YTE
M
ODE
As was previously discussed, in a single sync byte type write sequence, a minimum of 5 bytes of NRZ 93H and one byte
of 69H must be written between the end of the VCO sync field and the beginning of the user data. The 5 bytes of 93H
are 8,9 encoded and precoded during write mode to produce the adaptive equalizer training pattern. During read mode,
the encoded 93H sequence (100110011 read data sequence) and the encoded 69H are used to adaptively train the inner
two taps of the five tap transversal filter in a zero forcing manner. The error at the filter output is integrated to derive the
tap weight multiplying coefficient, Km1. Both of these inner taps use the same Km1. It is anticipated that the continuous
time filter will be used for coarse equalization and that transversal filter will be used adaptively for fine tuning. This will
reduce Km’s range and accuracy requirements. Since there are encoded user data patterns that will not produce an
equalizer correction error, an equalization hold during data mode can be selected from the Sample Loop Control
Register. If the equalizer is programmed to adapt only during the training sequence, the sync byte detect signal is used
to hold the Km1 value. After the training pattern, if the loop is active during user data, the equalizer loop gain will be
reduced by 7. The loop’s integration time constant is made inversely proportional to the selected data rate.
The Km1 coefficient can be held at the present instantaneous value by asserting the EQHOLD input. If EQHOLD is
asserted, the Km1 value will not be changed by either exiting read mode, subsequent training patterns, or by subsequent
data patterns. When EQHOLD is deasserted, the equalizer will resume its normally programmed functionality. The Km1
value can be held with reasonable accuracy for up to 1 ms to make the number of code periods required for acquisition
data rate independent.
T
RAINING
S
EQUENCE FOR
D
UAL
S
YNC
B
YTE
M
ODE
The adaptive equalizer training used for the dual sync byte detection mode is the same as that used in the single sync
byte mode except that the adaptation occurs over the 4 encoded 93H bytes, sync byte #1 (1FH), another 93H and sync
byte #2 (69H). This occurs because the Sync Byte Detect (SBD) is what disables the adaptation if adaptation is enabled
only during the training sequence. The number of consecutive 93H training bytes may be reduced in dual sync byte
mode because the sync byte #1 has been chosen to have the same training properties as the 93H training byte.
S
YNC
B
YTE
D
ETECT AND
NRZ O
UTPUT
The P32P4911A implements a dual "OR" type sync byte detection which offers increased sync byte detection capability
while maintaining backward compatibility with the single sync byte format and detection. The two bytes of the dual sync
byte are separated by a training byte to allow for Viterbi error propagation that may be caused by an error in the first sync
byte. The training byte 93H was chosen to provide the adaptive equalizer an ideal training signal.
As the read data is 8,9 decoded, it is compared to one of two internally fixed sync bytes (1FH or 69H). If the 1FH byte
is found, the SBD output will go Low 18 code clocks (2 byte times) later and the 69H byte will be the first non-zero byte
presented at the NRZ interface. If a match of the 69H byte is the first found, the sync byte detect (SBD) pin goes Low
and the NRZ output data that until now was held Low, is changed to 69H. The next byte presented on the NRZ outputs
is the first byte of user data. SBD will remain Low and NRZ data will continue to be presented at the NRZ interface until
the read gate is deasserted at which point SBD goes High and the NRZ outputs go to a high impedance state.
S
URFACE
D
EFECT
S
CAN
M
ODE
The P32P4911A helps check for media defects using the surface defect scan mode. In order to use this mode the part
must have the byte-wide interface enabled. In write mode, all zeros are presented (written) at the NRZ interface. When
this pattern is to be read back, bit 7 (DSE bit) of the N Counter Register is enabled which enables the surface defect scan
mode. The survival sequence register must also be turned off (BYPSR bit). In this mode, SBD will transition Low at SFC.
The NRZ7 pin is monitored. If no defect occurs, the NRZ7 pin will stay Low. If a defect occurs, the NRZ7 pin will transition
相關(guān)PDF資料
PDF描述
P3500SA SIDACtor Device
P3500S SIDACtor Device
P3500SCMC solid state crowbar devices
P3500SD solid state crowbar devices
P3500SC SIDACtor Device
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
P32P4F-F 制造商:TE Connectivity 功能描述:
P32RIGIDT 制造商:Brady Corporation 功能描述:SIGN NO UNAUTHORISED PERSONS 250X200
P32-S 制造商:Linemaster Switch Corporation 功能描述:Premier
P32W2A2-100-7 功能描述:膠帶 Acrylic Foam Tape 1/32" x 1" x 7YD RoHS:否 制造商:3M Electronic Specialty 產(chǎn)品:Tapes 類型:Shielding 描述/功能:EMI/RFI Foil Shielding Tape 顏色: 材料:Copper Foil 寬度:1 in x 18 yds
P32W2A2-100-72 功能描述:膠帶 Acrylic Foam Tape 1/32" x 1" x 72YD RoHS:否 制造商:3M Electronic Specialty 產(chǎn)品:Tapes 類型:Shielding 描述/功能:EMI/RFI Foil Shielding Tape 顏色: 材料:Copper Foil 寬度:1 in x 18 yds
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*