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參數(shù)資料
| 型號： | P32P4911A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 光電元器件 |
| 英文描述： | PRML Read Channel with PR4, 8/9 ENDEC, FWR Servo |
| 中文描述： | 1 CHANNEL READ CHANNEL, PQFP100 |
| 封裝： | 14 X 14 X 1.40 MM, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 25/63頁 |
| 文件大?。?/td> | 257K |
| 代理商： | P32P4911A |
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1996 Jul 25
25
Philips Semiconductors
Product specification
PRML Read Channel with PR4,
8/9 ENDEC, FWR Servo
P32P4911A
transmission and it should remain High until the completion of the transfer. At the end of each transfer SDEN should be
brought Low ("0").
When SDEN is High, the data presented to the Serial Data (SDATA) pin will be latched into the P32P4911A on each
rising edge of the Serial Clock (SCLK). Rising edges of SCLK should only occur when the desired bit of address or data
is being presented on the serial data line. Serial data transmissions must occur in 16-bit packets. If more than 16 rising
edges of SCLK are received during the time that SDEN is High, only the last 16 are considered valid. For all valid
transmissions, the data is latched into the internal register on the falling edge of SDEN.
Each 16-bit transmission consists of a read/write control bit (must always be reset, i.e., R/W = "0" for write only) followed
by 3 device select bits, 4 address bits and eight data bits. The device select and address bits select the internal register
to be written to. The device select, address and data fields are input LSB first, MSB last, where LSB is defined as Bit 0.
The three device select bits select the type of device on the Philips Semiconductors serial bus to be communicated with
and must be set to S0 = 0 or 1 (depending on register to be selected), S1 = 1, and S2 = 0 when communicating with the
P32P4911A. The figure below shows the serial interface timing diagram.
Description of Operating Modes
The fundamental operating modes of the P32P4911A are controlled by the Servo Gate (SG), Read Gate (RG), and Write
Gate (WG/WG) input pins. The exclusive assertion of any these inputs causes the device to enter that mode. If none of
these inputs is asserted, the device is in the idle mode. If more than one of the inputs is asserted, the mode is determined
by the following hierarchy: SG overrides RG which overrides WG/WG. The mode that is overriding takes effect
immediately.
RG and SG are asynchronous inputs and may be initiated or terminated at any position on the disk. WG/WG is also an
asynchronous input, but should not be terminated prior to the last output write data (WD/WD) pulse.
Figure 14: Serial Interface Timing
SDEN
SCLK
SDATA
t
C
t
SENS
t
CKL
t
CKH
t
DS
t
DH
t
SENH
t
SL
COMPLETE REGISTER STRING ID
R/W
“0”
S0
S1
S2
A0
A3
D0
D7
SM00003
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