參數(shù)資料
型號(hào)： P32P4911A
廠商： NXP SEMICONDUCTORS
元件分類： 光電元器件
英文描述： PRML Read Channel with PR4, 8/9 ENDEC, FWR Servo
中文描述： 1 CHANNEL READ CHANNEL, PQFP100
封裝： 14 X 14 X 1.40 MM, PLASTIC, LQFP-100
文件頁(yè)數(shù)： 6/63頁(yè)
文件大?。?/td> 257K
代理商： P32P4911A
1996 Jul 25
6
Philips Semiconductors
Product specification
PRML Read Channel with PR4,
8/9 ENDEC, FWR Servo
P32P4911A
FUNCTIONAL DESCRIPTION
The Philips Semiconductors P32P4911A implements a complete high performance PR4 read channel, including an
AGC, programmable filter/equalizer, adaptive transversal filter, Viterbi pulse qualifier, time base generator, data
separator with 8,9 ENDEC and scrambler/descrambler, and FWR servo, that supports data rates from 42 to 125 Mbit/s.
Data rates from 33 to 100 Mbit/s are supported by changing a single resistor.
A serial port is provided to write control data to the 17 internal program storage registers.
AGC Circuit Description
The automatic gain control (AGC) circuit is used to maintain a constant signal amplitude at the input of the pulse detector
and sampled data processor while the input to the amplifier varies. The circuit consists of an AGC loop that includes an
AGC amplifier, charge pump, programmable continuous time filter, and a precision, wide band, full wave rectifier.
Depending on whether the read is of servo or data type, the specific blocks utilized in the loop are slightly different. Both
loop paths are fully differential to minimize susceptibility to noise. AGC control can be programmably selected between
direct and timed modes.
AGC O
PERATION IN
S
ERVO
R
EAD
M
ODE
During servo reads the loop consists of the AGC amplifier with a continuous dual rate charge pump, the programmable
continuous time filter, and the full wave rectifier. The gain of the AGC amplifier is controlled by the voltage stored on the
BYPS hold capacitor (C
BYPS
). The dual rate charge pump drives C
BYPS
with currents that drive the differential voltage
at DP/DN (internal nodes) to the value programmed by the 2 SAGCLVL bits in the LDS register. These 2 bits allow
adjustment of the filter's normal output voltage from 1.10 to 1.40 Vppd. Attack currents lower the voltage at the BYPS
pin which reduces the amplifier gain. Decay currents raise the voltage at the BYPS pin which increases the amplifier
gain. The sensitivity of the amplifier gain to changes in the BYPS voltage is approximately 38 dB/V. When the voltage
at BYPS is equal to VRC, the gain from the AGC input to DP/DN will be about 24.9 dB. The charge pump is continuously
driven by the instantaneous voltage at DP/DN. When the signal at DP/DN is greater than 100% of the programmed AGC
level, the normal attack current (I
CH
) of 416.5
μ
A is used to reduce the amplifier gain. If the signal is greater than 125%
of the programmed level, the fast attack current (I
CHF
) of 3.5 mA is used to reduce the gain very quickly. This dual rate
approach allows the AGC gain to be quickly decreased when it is too high and minimizes distortion when the proper AGC
level has been acquired. The 100% and 125% levels are relative to the selected AGC level in servo mode.
A constant normal decay current (I
D
) of 24.5
μ
A acts to increase the amplifier gain when the signal at DP/DN is less than
100% of the programmed AGC level. The large ratio (416.5
μ
A:24.5
μ
A) of the normal attack and normal decay currents
enables the AGC loop to respond to the peak amplitudes of the incoming read signal rather than the average value. As
a result the AGC loop will not be able to quickly increase its gain if required to do so. A fast recovery mode is provided
to allow the gain to be rapidly increased to reduce recovery time between mode switches. In the fast recovery mode, the
decay current is increased by a factor of 8 to 196
μ
A (I
DFR
) and the attack current is increased by a factor of 4.18 to
1.74 mA (I
CHFR
). This has the effect of speeding up the AGC loop between 4 and 8 times.
It is recommended that the fast recovery mode be asserted when the AGC fields from a sector are being read. Typically,
this will be just after each transition of SG (Servo Gate), after powerup, and after WG/WG is de-asserted. For example,
if C
BYPS
is 500 pF and FASTREC is asserted for 0.5
μ
s in servo mode, the voltage at BYPS can increase at most by
0.5
μ
s * 196
μ
A/500 pF = 196 mV, which will allow the gain to increase by 6 dB in that time. If FASTREC is asserted for
0.5
μ
s in non-servo mode and C
BYP
is 1000 pF, then the voltage at BYP can increase at most by 0.5
μ
s * 196
μ
A/
1000 pF = 98 mV, which will allow the gain to increase by 3 dB in that time. It is recommended that LOWZ be asserted
for 0.5
μ
s just prior to any assertion of FASTREC in order to null any internal DC offsets. However, it is possible to assert
both LOWZ and FASTREC simultaneously to reduce sector overhead. This method should be evaluated under the
actual system operating conditions.
The programmable AGC level in servo mode is provided to allow the servo demodulator dynamic range to be adjusted
over a narrow range.
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