參數(shù)資料
型號(hào)： P32P4911A
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 光電元器件
英文描述： PRML Read Channel with PR4, 8/9 ENDEC, FWR Servo
中文描述： 1 CHANNEL READ CHANNEL, PQFP100
封裝： 14 X 14 X 1.40 MM, PLASTIC, LQFP-100
文件頁(yè)數(shù)： 22/63頁(yè)
文件大?。?/td> 257K
代理商： P32P4911A
1996 Jul 25
22
Philips Semiconductors
Product specification
PRML Read Channel with PR4,
8/9 ENDEC, FWR Servo
P32P4911A
S
INGLE
S
YNC
B
YTE
D
ETECTION WHEN
S
EMI
A
UTOMATIC
T
RAINING
I
S
E
NABLED
When the AUTOTR bit is set in the Control Operating Register, the training/sync byte sequence is generated with an
internal state machine. The internal state machine generates the 5-byte equalizer training pattern (93H) followed by the
second sync byte (69H); the first sync byte (1FH) is not written by the internal state machine. To initiate the writing of
the training pattern and sync byte in this mode, an FFH must be placed on the NRZ bus for 6 byte times prior to the user
data. This mode may be desirable if controller state machine space is very limited.
S
CRAMBLER
/D
ESCRAMBLER
The scrambler/descrambler circuit is provided to reduce fixed pattern effects on the channel's performance. It is enabled
or disabled by bit 2 (SD) of the Control Operating Register. In write mode, if enabled, the circuit scrambles the 8-bit
internal NRZ data before passing it to the encoder. Only user data, i.e., the NRZ data following the second sync byte
(69H), is scrambled. In data read mode, only the decoded NRZ data after the second sync byte (69H) is descrambled.
The scrambler polynomial is H(X)= 1
⊕
X7
⊕
X10. The scrambler block diagram is shown in Figure 10. The scrambler
contributes no delay in either the encode or decode paths and therefore there is no difference in path delays whether or
not the scrambler is enabled.
NRZ I
NTERFACE
The NRZ interface circuit provides the ability to interface with either a nibble or byte-wide controller. The NRZ interface
type is specified by the programming of bit 4 (NIB) of the Control Operating Register. If byte-wide mode is selected, the
circuit does not reformat the data before passing it to and from the internal 8-bit bus. If nibble mode is selected, the NRZ
interface circuit converts the 4 LSBs of the external 8-bit bus to the internal 8-bit bus. Only the selected NRZ interface
is enabled and the unused bits can be left floating. Both the byte-wide and nibble interfaces define the most significant
bit of the interface as the most significant bit of the data and the nibble interface defines the first nibble clocked in or out
as the most significant of the pair.
For both byte-wide and nibble operation, the NRZ write data is latched by the P32P4911A on the rising edge of the WCLK
input. The WCLK frequency must be appropriate for the data rate chosen or else overflow/underflow will occur. It is
recommended that WCLK be connected to RCLK to prevent this from occurring. In byte-wide mode, as each NRZ byte
is input to the P32P4911A, its parity is checked against the controller supplied parity bit NRZP.
In data read mode, the NRZ data will be presented to the controller near the falling edge of RCLK so that it can be latched
by the controller on the rising edge of RCLK. When RG goes High, the selected NRZ interface will output Low data until
the sync byte has been detected. The first non-zero data presented will be the sync byte (69H). The NRZ interface is
Figure 10: P32P4911A Scrambler Block Diagram
X0
X1
X2
X3
X4
X5
X6
X7
X8
X9
XOR
NRZ0-7
SCRAM0-7
XOR
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