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參數(shù)資料
| 型號： | P32P4911A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 光電元器件 |
| 英文描述： | PRML Read Channel with PR4, 8/9 ENDEC, FWR Servo |
| 中文描述： | 1 CHANNEL READ CHANNEL, PQFP100 |
| 封裝： | 14 X 14 X 1.40 MM, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 31/63頁 |
| 文件大?。?/td> | 257K |
| 代理商： | P32P4911A |
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1996 Jul 25
31
Philips Semiconductors
Product specification
PRML Read Channel with PR4,
8/9 ENDEC, FWR Servo
P32P4911A
High on the falling edge of RCLK and stay high as long as the defect is present, transition back Low on the next falling
edge of RCLK when the defect is not present.
Power Down Operation
The power management modes of the P32P4911A are determined by the states of the Power Down Register bits and
the PDWN and SG inputs. The individual sections of the chip can be powered down or up using the Power Down
Register. A High level in a Power Down Register bit disables that section of the circuit. The power down information
from the Power Down Register takes effect immediately after the SDEN pin goes Low.
When the PDWN input is Low, the chip goes into full power down mode regardless of the power down register settings
or the state of the SG input.
When PDWN is High, SG will force the AGC, filter, and pulse qualifier circuits (front end) to be active by overriding the
front end register bit. The back end power down register bits, which include the Data Separator and Time Base Generator
are not affected by the SG input.
The serial port is active in all power down modes.
The time to restart from a full power down is dependent on the PLL loop filter and the data rate.
The truth table for the various modes of operation is shown below:
SG, PDWN :
Front End
Data Separator
Time Base Generator
Serial Port
1,1
ON
R
R
ON
1,0
OFF
OFF
OFF
ON
0,1
R
R
R
ON
0,0
OFF
OFF
OFF
ON
R =
Controlled by register bit.
(Register bit =1 turns circuits OFF,
Register bit = 0 turns circuits ON)
Figure 18: Surface Defect Scan Mode
SFC
RG
SBD
RCLK
NRZ7
DEFECT
SM00002
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