參數(shù)資料
型號(hào)： P32P4911A
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 光電元器件
英文描述： PRML Read Channel with PR4, 8/9 ENDEC, FWR Servo
中文描述： 1 CHANNEL READ CHANNEL, PQFP100
封裝： 14 X 14 X 1.40 MM, PLASTIC, LQFP-100
文件頁(yè)數(shù)： 44/63頁(yè)
文件大?。?/td> 257K
代理商： P32P4911A
1996 Jul 25
44
Philips Semiconductors
Product specification
PRML Read Channel with PR4,
8/9 ENDEC, FWR Servo
P32P4911A
Digital Input Pins (Continued)
Pin Name
Type
Pin Function
DWI, DWI
I
DIRECT WRITE INPUTS: Inputs connect to the toggle input of the write data flip-flop
when DWR is Low. PECL input levels. Can be left open.
SERVO REFERENCE SELECT: TTL compatable input. When SG is low, this input
determines where SREF (SELVRC=high) or SREF + 200 mV (SELVRC = low) is
presented at SREF output. An open pin is logic high.
SERVO TEST MODE: TTL compatible input that enables an internal pulldown current at
the SREF and SEROUT pins. An open pin is logic high.
SELVRC
I
SDIEN
I
Digital Bi-directional Pins
Pin Name
Type
Pin Function
NRZ0-7
I/O
BYTE WIDE NRZ DATA PORT: TTL compatible CMOS bi-directional input/output. Input
to the encoder when WG/WG is High. Output from the decoder when RG is High. The 4
LSBs are used in nibble mode. The 4 MSBs can be left open if not used.
NRZ DATA PARITY BIT: Active when in Byte-Wide mode. TTL compatible CMOS
bi-directional input / output. Generates even read parity when RG is High, and accepts
even write parity when WG/WG is active. Can be left open if not used.
NRZP
I/O
Digital Output Pins
Pin Name
Type
Pin Function
RCLK
O
READ REFERENCE CLOCK: A multiplexed clock source used by the controller. When
RG is Low, RCLK is synchronized to the time base generator output, F
TBG
. When RG goes
High, RCLK remains synchronized to F
TBG
until the SFC is reached. At that time, RCLK is
synchronized to the data separator VCO. During a mode change, no glitches are
generated and no more than one lost clock pulse will occur. Limited swing CMOS output
levels.
NIBBLE MODE CLOCK: A half byte clock synchronized to RCLK. It runs at twice the
frequency of RCLK. Limited swing CMOS output levels. Signal present in byte-wide mode.
SYNC BYTE DETECT: Transitions Low upon detection of sync byte. This transition is
synchronous with the sync byte's placement on the NRZ lines. Once it transitions Low,
SBD remains Low until RG goes Low, at which point it returns High. CMOS output.
WRITE DATA: Write data flip-flop output. The data is automatically re-synchronized
(independent of the delay between RCLK and WCLK) to the reference clock F
TBG
, except
in Direct Write mode 2. Differential PECL output levels.
SERVO READ DATA: Read Data Pulse output for servo read data. Active Low limited
swing CMOS output. Output active when SG is High, and High when SG is Low. The
RDS/RDS output becomes active High if the Servo Mode Select bit (SMS) in the Data
Rate Register is set.
SERVO READ DATA POLARITY: Read Data Pulse polarity output for servo read data.
Active High limited swing CMOS output. Negative pulse = Low, positive pulse = High.
Output active when SG is High.
NCLK
O
SBD
O
WD, WD
O
RDS/RDS
O
PPOL
O
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