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參數(shù)資料
| 型號： | P32P4911A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 光電元器件 |
| 英文描述： | PRML Read Channel with PR4, 8/9 ENDEC, FWR Servo |
| 中文描述： | 1 CHANNEL READ CHANNEL, PQFP100 |
| 封裝： | 14 X 14 X 1.40 MM, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 43/63頁 |
| 文件大?。?/td> | 257K |
| 代理商： | P32P4911A |
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1996 Jul 25
43
Philips Semiconductors
Product specification
PRML Read Channel with PR4,
8/9 ENDEC, FWR Servo
P32P4911A
Digital Input Pins
Pin Name
Type
Pin Function
LOWZ
I
Low-Z MODE INPUT: TTL compatible CMOS control pin which, when pulled High, the input
impedance is reduced to allow rapid recovery of the input coupling capacitor. When pulled
Low, keeps the AGC amplifier and filter input impedance high. An open pin is a logic High.
FAST RECOVERY: TTL compatible CMOS control pin which, when pulled High, puts the
AGC charge pump in the fast decay mode. An open pin is a logic High.
POWER DOWN CONTROL: CMOS compatible power control pin. When set to logic
Low, the entire chip is in sleep mode with all circuitry, except serial port, shut down. This
pin must be set to logic High in normal operating mode. Selected circuitry can be shut
down by the Power Down Register. The PDWN pin must be either driven to a valid
CMOS High level or externally pulled up since it is not internally pulled up.
AGC HOLD CONTROL INPUT: TTL compatible CMOS control pin which, when pulled
Low, holds the AGC amplifier gain constant by turning off the AGC charge pump. The
AGC loop is active when this pin is either at High or open.
EQUALIZER HOLD CONTROL INPUT: TTL compatible control pin which, when pulled
High causes the present adaptive equalizer tap weights to be held until the input is set
Low. An open pin is at logic High.
REFERENCE FREQUENCY INPUT: Reference frequency for the time base generator.
FREF may be driven either by a direct coupled TTL signal or by an ac coupled ECL
signal. When bit 3 (BT) of the Control Operating Register (CM1) is set, FREF replaces
the VCO as the input to the data separator.
WRITE CLOCK: TTL compatible CMOS input that latches in the data at the selected
NRZ interface on the rising edge. Must be synchronous with the write data NRZ input.
For short cable delays, WCLK may be connected directly to pin RCLK. For long cable
delays, WCLK should be connected to an RCLK return line matched to the NRZ data bus
line delay. An open pin is at logic High.
READ GATE: TTL compatible CMOS input that, when pulled High, selects the PLL
reference input and initiates the PLL synchronization sequence. A High level selects the
RD input and enables the read mode/address detect sequences. A Low level selects the
time base generator output. An open pin is at logic High.
WRITE GATE: TTL compatible CMOS input that, when pulled High, enables the write
mode. The active state of WG/WG can be selected by the WGP bit in the control
operating register. An open pin is at logic High.
SERVO GATE: TTL compatible CMOS input that, when pulled High, enables the servo
read mode. An open pin is at logic High.
VITERBI READ DATA: A TTL or ac coupled PECL compatible input to the data separator
back end, for testing purposes only. This pin is controlled by the VRDT bit in the Control
Test Register (CT).
DIRECT WRITE MODE 2 ENABLE: Enables DWI, DWI inputs to the write data flip-flop
when input is Low. TTL compatible CMOS levels. Open pin is at logic High.
FASTREC
I
PDWN
I
HOLD
I
EQHOLD
I
FREF
I
WCLK
I
RG
I
WG/WG
I
SG
I
VRDT
I
DWR
I
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