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參數資料
| 型號： | P32P4911A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 光電元器件 |
| 英文描述： | PRML Read Channel with PR4, 8/9 ENDEC, FWR Servo |
| 中文描述： | 1 CHANNEL READ CHANNEL, PQFP100 |
| 封裝： | 14 X 14 X 1.40 MM, PLASTIC, LQFP-100 |
| 文件頁數： | 39/63頁 |
| 文件大小： | 257K |
| 代理商： | P32P4911A |
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1996 Jul 25
39
Philips Semiconductors
Product specification
PRML Read Channel with PR4,
8/9 ENDEC, FWR Servo
P32P4911A
Serial Port Register Definitions (Continued)
Complete Register ID String
A3
A2
A1
A0
S2
S1
S0
R/W
Sample Loop Control
Register (SLC)
1
1
1
0
0
1
0
0
E4H
Bit 7
RDSPW
RDS output pulse width
0 = 15 ns
1 = 27 ns
Sync Field Count
Sync Field Count (code clocks)
64
80
96
128
Adaptive Equalizer Loop time constant shift
0 = equalizer loop time constant same in preamble and data
fields
1 = equalizer loop time constant is increased to 7X in the
data field elative to the preamble field, i.e. loop gain is
reduced to 1/7
Enable Adaptive Equalizer on Data Field
0 = adaptive equalizer disabled after preamble field
1 = adaptive equalizer in use after preamble field,
if AEE bit = 1
Enable Adaptive Equalizer
0 = adaptive equalizer disabled
1 = adaptive equalizer enabled for use in preamble field,
and after the preamble field if AED bit = 1
AGC charge pump current in Sampled AGC mode
AGC charge/discharge current (
μ
A) = 2.66 * AGC * DR/RR
(k
)
37 < DR < 127, e.g., RR = 10 k
e.g., for DR = 100 and
AGC=10 =2
dec
charge pump current = 53
μ
A
1
1
0
1
Data separator PLL gain shift factor
0 = 6
1 = 10
Damping amplifier gain A = D * (0.7 / 127)
Damping Ratio =
A
0.25
×
ω
n
Bits 6-5
SFC1
0
0
1
1
Bit 4
SFC1-0
SFC0
0
1
0
1
AEGS
Bit 3
AED
Bit 2
AEE
Bits 1-0
AGC1-0
Damping Ratio Control
Register (DRC)
1
Bit 7
1
GS_10
0
0
F4H
Bits 6-0
D6-0
----------K2
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