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參數(shù)資料
| 型號： | P32P4911A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 光電元器件 |
| 英文描述： | PRML Read Channel with PR4, 8/9 ENDEC, FWR Servo |
| 中文描述： | 1 CHANNEL READ CHANNEL, PQFP100 |
| 封裝： | 14 X 14 X 1.40 MM, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 23/63頁 |
| 文件大小： | 257K |
| 代理商： | P32P4911A |
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1996 Jul 25
23
Philips Semiconductors
Product specification
PRML Read Channel with PR4,
8/9 ENDEC, FWR Servo
P32P4911A
at a high impedance state when not in data read mode. In byte-wide mode, an even parity bit , NRZP, is generated for
each output byte.
W
RITE
P
RECODER
The P32P4911A implements a 1/(1
⊕
D
2
) write precoder which is used to precode the serialized encoder data for PR4.
The state of the precoder is preset to 0,0 upon exiting write mode. This guarantees that precoder will begin the next write
in the 0,0 state. The state of the precoder is not guaranteed when the write data (WD/WD) changes from sync field to
encoded data. The result is that one of 2 different write data patterns or their inverses may be written for a particular
write. All four of these patterns will decode properly upon read back. As a result of the fact that the write data toggle
flip-flop is utilized as part of the precoder, the read/write amplifier connected to the P32P4911A must not contain a T
flip-flop. The precoder block diagram is shown in Figure 12.
Figure 11: NRZ Timing
RCLK
NRZ0-7
Read Mode-Byte Wide
byte 0
byte 1
WCLK
NRZ0-7
Write Mode-Byte Wide
byte 0
byte 1
RCLK
Read Mode-Nibble
NRZ1
bit 5
bit 4
bit 0
NRZ0
WCLK
NRZ1
bit 5
bit 4
bit 0
Write Mode-Nibble
bit 4
NRZ0
bit 7
bit 5
bit 3
bit 1
bit 7
NRZ3
bit 6
bit 2
bit 6
NRZ2
NRZ3
bit 7
bit 5
bit 3
bit 1
bit 7
bit 6
bit 4
bit 2
bit 6
NRZ2
byte 0 = MSN
byte 0 = LSN
byte 1 = MSN
byte 0 = MSN
byte 0 = LSN
byte 1 = MSN
Figure 12: Precoder Block Diagram
D
XOR
WRITE CURRENT
CODED DATA
D
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