參數(shù)資料
型號(hào)： P32P4911A
廠商： NXP SEMICONDUCTORS
元件分類： 光電元器件
英文描述： PRML Read Channel with PR4, 8/9 ENDEC, FWR Servo
中文描述： 1 CHANNEL READ CHANNEL, PQFP100
封裝： 14 X 14 X 1.40 MM, PLASTIC, LQFP-100
文件頁數(shù)： 28/63頁
文件大小： 257K
代理商： P32P4911A
1996 Jul 25
28
Philips Semiconductors
Product specification
PRML Read Channel with PR4,
8/9 ENDEC, FWR Servo
P32P4911A
a total of 6 byte times. Note that the semi-automatic mode can only be used to write single sync byte format and the
training pattern length is fixed at 5. This mode is useful if controller state machine space is extremely limited.
U
SER
D
ATA
The user data must be presented at the NRZ interface immediately following the last NRZ sync byte written. Finally, after
the last byte of user data has been clocked in, the WG/WG must remain active for a minimum of 16 NRZ bit times in
byte-wide mode to ensure the that the device is flushed of data (The delay is 21 NRZ bit times in nibble mode). WG/WG
can then go inactive. WD/WD stops toggling a maximum of 2 NRZ (RCLK) time periods after WG/WG goes inactive.
D
IRECT
W
RITE
M
ODE
#1
In this direct write mode, the NRZ data from the byte-wide interface bypasses the scrambler, the 8,9 encoder and the
precoder, but is precompensated before going to the write data flip-flop and then to the WD/WD output pins. The RCLK
output is changed from 9 VCO clock periods to 8 VCO clock periods with a 3/8 duty cycle. The purpose of routing the
signal to the precomp circuit is to generate a return to zero pulse every time a "1" occurs in the data so that the write data
flip-flop is toggled. WCLK is not required to latch the byte-wide NRZ data into the NRZ interface since the data is latched
by an internal version of RCLK, but the NRZ data must be valid no later than 12 ns after the rising edge of the RCLK
output pin. Direct write mode #1 is selected by setting the DW bit (bit 0) in the Control Operating Register. and is entered
when the WG/WG input is active. This mode is not valid when using the nibble NRZ interface. Note that Direct Write
Mode #2 will override Direct Write Mode #1.
D
IRECT
W
RITE
M
ODE
#2
In this direct write mode, the data presented at the DWI/DWI input pins directly toggles the write data flip-flop which drives
the WD/WD output pins. No WCLK is required in this mode, and the WD/WD output is not resynchronized. Direct write
mode #2 is selected by driving the DWR input Low and is entered when the WG/WG input is active. Note that the Direct
Write Mode #2 will override Direct Write Mode #1.
D
ATA
R
EAD
M
ODE
O
PERATION
Data read mode is initiated by setting the Read Gate (RG) input pin High. This action causes the data synchronizer to
begin acquisition of the clock from the incoming VCO sync pattern. To achieve this, the data synchronizer utilizes a fully
integrated fast acquisition PLL to accurately develop the sample clock. This PLL is normally locked to the time base
Figure 16: Hard Sector Semi-Auto Write Mode
GAP
8 BYTES MIN.
5 BYTES
1 BYTE
NRZ DATA (WRITTEN TO 4911A)
00H
FFH
FFH
USER DATA
WG
NRZ DATA (WRITTEN BY 4911A)
00H
93H
69H
USER DATA
VCO SYNC
FIELD
TRAINING
SEQUENCE
SYNC
BYTE
SCRAMBLED AND ENCODED
USER DATA
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