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參數(shù)資料
| 型號： | P32P4911A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 光電元器件 |
| 英文描述： | PRML Read Channel with PR4, 8/9 ENDEC, FWR Servo |
| 中文描述： | 1 CHANNEL READ CHANNEL, PQFP100 |
| 封裝： | 14 X 14 X 1.40 MM, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 7/63頁 |
| 文件大?。?/td> | 257K |
| 代理商： | P32P4911A |
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1996 Jul 25
7
Philips Semiconductors
Product specification
PRML Read Channel with PR4,
8/9 ENDEC, FWR Servo
P32P4911A
AGC O
PERATION IN
D
ATA
R
EAD
M
ODE
For data reads, the loop described above is used until the data synchronizer is locked to the incoming VCO preamble,
except that the BYP hold capacitor (C
BYP
) is used instead of BYPS and (C
BYPS
). The normal decay current is 24.5
μ
A,
the normal attack current is 416.5
μ
A, and the fast attack current is 3.5 mA. The fast recovery mode decay current is
196
μ
A and the fast recovery mode attack current is 1.74 mA. The above mentioned attack and decay currents are not
scaled with the data rate setting. After the data synchronizer PLL is locked (SFC), the AGC loop is switched to include
the AGC amplifier with a sampled charge pump, the programmable continuous time filter, full wave rectifier, and the
sampling 5-tap equalizer to more accurately control the signal amplitude into the Viterbi qualifier. In this sampled AGC
mode, a symmetrical attack and decay charge pump is used. The "1" sample amplitudes are sampled and held and
compared to the ideal "1" value of 500 mV to generate the error current. The maximum charge pump current value can
be programmed from the Sample Loop Control Register to 0, 34, 68, or 102
μ
A for maximum data rate and will scale
downward with reduced Data Rate Register values.
AGC Control Modes
The AGC control mode is determined by the state of bit 6 (AGCSEL) of the Control Operating Register #1. If this bit is
0, then the direct, external AGC control method is selected, i.e., AGC uses external signals provided to the FASTREC,
LOWZ, and HOLD input pins. If bit 6 is a 1, the timed AGC control method is selected for generating the internal hold,
fast recovery, squelch, and Low-Z signals.
D
IRECT
AGC C
ONTROL
M
ODE
For maximum application flexibility, all AGC mode control inputs are to be externally provided. When the LOWZ input is
High, Low-Z mode is activated. In the Low-Z mode, the AGC amplifier input resistance is reduced to allow quick recovery
of the AGC amplifier input AC coupling capacitors. The ratio of Low-Z to Non Low-Z resistance can be selected as either
15:1 or 5:1 by programming the LZTC bit in the Data Boost Register. During Low-Z mode, the time constant of the
internal AC coupling networks at the filter outputs are also reduced by the ratio determined by the LZTC bit. This time
constant is 300 ns in Low-Z and either 5
μ
s or 1.5
μ
s when not in Low-Z mode, depending on the state of the LZTC bit.
Low-Z also forces the AGC amplifier gain to be reduced to near 0 V/V. This mode should be activated during and for a
short time after a write operation. It should also be activated for a short time after each transition of the SG input and on
initial power up.
When theHOLD input is Low, the charge pumps are disabled. This de-activates the AGC loop. The AGC amplifier gain
will be held constant at a level set by the voltage at the BYP or BYPS pins. The value of the capacitor placed at these
pins should be selected to give adequate droop performance when in hold mode as well as to insure stability of the AGC
loop when it is active.
The signal provided to the FASTREC input pin determines if the AGC is in fast recovery mode. During the fast recovery
(FASTREC=1), the attack and decay currents are increased to allow faster recovery to the proper AGC level. If faster
recovery than is provided by FASTREC alone is desired, an ultra fast recovery can be effected by connecting a resistor
between the AGCRST pin and the positive supply VPA. If this resistor is present, whenever FASTREC is entered, the
voltage on the BYP or BYPS capacitor will be pulled up. This causes an extremely rapid increase in the AGC amplifier
gain. The ultra fast current will be disabled the first time that the signal at DP/DN reaches the 125% point. The FASTREC
attack and decay currents are used as long as the FASTREC pin is held High.
T
IMED
AGC C
ONTROL MODE
This timed AGC control mode differs from the direct control mode in that the external control inputs LOWZ, FASTREC,
and HOLD, are typically not used, and therefore, must be deasserted. The equivalent signals are generated internal to
the P32P4911A. These internal signals are generated by one-shots that are triggered by various conditions of the
WG/WG, SG, and PDWN inputs. The one-shot timings for the Low-Z and fastrec signals are set by the resistors
connected to the WRDEL and AGCDEL input pins, respectively and analog ground. The time Low-Z period = 0.1
μ
s *
(R
WRDEL
+ 0.5) k
and the fast recovery period = 0.1
μ
s * (R
AGCDEL
+ 0.5) k
.
The current for the ultra fast decay mode
is set by the resistor connected between the AGCRST input pin and VPA. In the timed mode, the AGC shall use the
C
BYP
and C
BYPS
for non-servo and servo modes respectively. The nominal and fast attack and decay currents are the
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