參數(shù)資料
型號： P32P4911A
廠商： NXP SEMICONDUCTORS
元件分類： 光電元器件
英文描述： PRML Read Channel with PR4, 8/9 ENDEC, FWR Servo
中文描述： 1 CHANNEL READ CHANNEL, PQFP100
封裝： 14 X 14 X 1.40 MM, PLASTIC, LQFP-100
文件頁數(shù)： 33/63頁
文件大?。?/td> 257K
代理商： P32P4911A
1996 Jul 25
33
Philips Semiconductors
Product specification
PRML Read Channel with PR4,
8/9 ENDEC, FWR Servo
P32P4911A
Servo Filter Cutoff Register
(FCS)
0
Bit 7
0
PDM
1
Servo Peak Detector Mode
0 = Window Qualifier
1 = Hysteresis Qualifier
Filter cutoff frequency setting in servo mode
c (MHz) = 0
.
277 * FC + 0.0802 14 < FC < 43
dec
1
1
0
Non Low-Z vs. Low-Z time constant
0 = 15:1
1 = 5:1
Filter boost setting in data mode
Boost (dB) = 20 * log[0.021848 * FB + 0.000046 * FB * FC + 1]
0 < FB < 127
dec
0
0
0
1
Filter boost setting in servo mode
00 = 0 dB
01 = 2 dB
10 = 4 dB
11 = 6 dB
Filter Group Delay
% In all modes
Group Delay
% = 0.9783 * (FGD 4-0) - 0.665,
where FGD5 = 1 is positive, 0 is negative
0
≤
FGD
≤
31
dec
0
1
0
1
Survival Sequence Register Bypass/Write Precode Bypass
0 = bypass disabled (normal operation)
1 = bypass enabled
Viterbi qualification threshold voltage
Vth (mV) = 7.874 * VD
45
≤
VD
≤
127
dec
1
0
0
1
Not used
Data level qualification threshold voltage
if WP/LT Register : ALE = 0 (Fixed levels)
Prior to SFC : Lth (mV) = 10.47 * LD
After SFC : Lth (mV) = 7.44 * LD
16
≤
LD
≤
63
dec
if WP/LT Register : ALE = 1 (Adaptive levels)
After SFC : Lth (%) = 1.574 * LD
0
0
1
0
0
24H
Bits 6-0
FCS6-0
Data Filter Boost Register (FB)
0
Bit 7
0
LZTC
1
0
0
34H
Bits 6-0
FB6-0
Servo Filter Boost Register
(FBS) and Group Delay
Equalizer Register
0
Bits 7-6
1
FBS 1-0
0
0
44H
Bits 5-0
FGD5-0
Viterbi Detector Threshold
Register (VDT)
0
Bit 7
1
BYPSR
0
0
54H
Bits 6-0
VD6-0
Data Level Threshold Register
(LD)
0
BIts 7-6
Bits 5-0
1
0
0
64H
LD5-0
Serial Port Register Definitions (Continued)
Complete Register ID String
A3
A2
A1
A0
S2
S1
S0
R/W
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