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參數(shù)資料
| 型號： | P32P4911A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 光電元器件 |
| 英文描述： | PRML Read Channel with PR4, 8/9 ENDEC, FWR Servo |
| 中文描述： | 1 CHANNEL READ CHANNEL, PQFP100 |
| 封裝： | 14 X 14 X 1.40 MM, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 26/63頁 |
| 文件大?。?/td> | 257K |
| 代理商： | P32P4911A |
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1996 Jul 25
26
Philips Semiconductors
Product specification
PRML Read Channel with PR4,
8/9 ENDEC, FWR Servo
P32P4911A
Mode Control
WG/WG
I
DLE
M
ODE
O
PERATION
If SG, RG, and WG/WG are not active, the P32P4911A is in idle mode. When in idle mode, the Time Base Generator
and the Data Separator PLL are running and the Data Separator PLL is phase-frequency locked to the TBG VCO output.
The AGC, continuous time filter, and pulse qualifiers are active but the outputs of the pulse qualifiers are disabled. The
continuous time filter is using its programmed values for cutoff frequency and boost determined by the data mode
registers. The AGC operation is the same as in the VCO preamble portion of a data read. Servo burst capture is
operational in idle mode but the filter and AGC settings are for data reads and not for servo reads as would be the case
if the device was in servo mode. The RDS/RDS and PPOL outputs are disabled in idle mode.
S
ERVO
M
ODE
O
PERATION
If SG is High, the device is in the servo mode. This mode is the same as idle except that the filter cutoff and boost settings
are switched from those programmed for data read mode to those programmed for servo mode, the AGC is switched to
servo mode, and the RDS/RDS and PPOL and outputs are enabled. The assertion of SG causes read mode, write mode,
and the power down register settings for the front end to be overridden.
W
RITE
M
ODE
O
PERATION
The P32P4911A supports three different write modes; Normal write mode, direct write mode #1 and direct write mode
#2. The direct write modes require that either the direct write bit, bit 0 of the Control Operating Register, or the DWR pin
be active. All three write modes require that the Data Separator be powered on. The active polarity of write gate can be
selected by programming the WGP bit in the Control Operating Register. The PDWN input should be kept Low until all
registers are properly loaded to prevent an illegal write operation at power up.
N
ORMAL
W
RITE
M
ODE
The P32P4911A is in the normal write mode if WG/WG is active, DWR is High, and the direct write bit in the Control
Operating Register is Low. A minimum of one NRZ time period must elapse after RG goes Low before WG/WG can be
set active. The Data Separator PLL is phase-frequency locked to the TBG VCO output in this mode.
In normal write mode, the circuit first autogenerates the VCO sync pattern, then scrambles the incoming NRZ data from
the controller, encodes it into 8,9 GCR formatted data, precodes it, precompensates it, feeds it to a write data toggle
flip-flop, and outputs it to the preamp for storage on the disk. When WG/WG goes inactive, the WD/WD outputs remain
enabled but the active pull down current is reduced by a factor of 7 to reduce power consumption and the write data
flip-flop is reset to guarantee that the WD/WD outputs represent a zero state.
In normal write operation, when the write gate (WG/WG) goes active, the VCO sync field generation begins, which
causes a continuous "2T" pattern at the WD/WD outputs {(1,1,-1,-1,1,1,-1,-1...) in the write current domain}. The NRZ
inputs must be Low and must be held Low for the duration of the VCO sync field generation. The minimum required sync
field is equivalent to 8 byte times.
RG
DEVICE MODE
DESCRIPTION
0/1
0/1
0
1
Idle Mode
Data Read
Mode
DS VCO locked to F
TBG
. NRZ7-0 tri-stated.
DS PLL acquisition, adaptive equalizer training, code word boundary
search and detect, decode, sync byte detect, and NRZ data output. DS
VCO switched from F
TBG
to RD after preamble detect. RCLK gen. input
switched from F
TBG
to DS VCO. RCLK re-synchronized to RD at code
word boundary detect. NRZ7-0 active.
Data Write Mode Write mode preamble insertion and data write. DS VCO locked to F
TBG
.
RCLK synchronized to F
TBG
. WD and WD active. NRZ7-0 = inputs.
Read Override
RG overrides WG/WG which causes any write in progress to cease and
Data Read Mode to be entered.
1/0
0
1/0
1
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