參數(shù)資料
型號: 82815EM
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù): 108/163頁
文件大?。?/td> 1049K
代理商: 82815EM
Intel
82815EM GMCH
R
108
Datasheet
3.8.23.
PM_CAPID—Power Management Capabilities ID Register
(Device 2)
Address Offset:
DCh
DDh
Default Value:
0001h
Access:
Read Only
15
8
7
0
NEXT_PTR
CAP_ID
Bits
Description
15:8
NEXT_PTR.
This contains a pointer to next item in capabilities list. This the final capability in the list
and must be set to 00h.
7:0
CAP_ID.
SIG defines this ID is 01h for power management.
3.8.24.
PM_CAP—Power Management Capabilities Register (Device 2)
Address Offset:
DEh
DFh
Default Value:
0022h
Access:
Read Only
15
11
10
9
8
PME Support (HW=0)
D2
(HW=0)
D1
(HW=0)
Reserved
7
6
5
4
3
2
0
Reserved
Dev
Specific
Init
(HW=1)
Aux Pwr
Src
(HW=0)
PME
Clock
(HW=0)
Version
Bits
Description
15:11
PME Support.
This field indicates the power states in which GMCH2-M may assert PME#. Hardwired
to 0 to indicate that GMCH2-M does not assert the PME# signal.
10
D2.
Hardwired to 0 to indicate D2 power management state is not supported.
9
D1.
Hardwired to0 to indicate that D1 power management state is NOT supported.
8:6
Reserved.
Read as 0s.
5
Device Specific Initialization (DSI).
Hardwired to 1 to indicate that special initialization of GMCH2-M
is required before generic class device driver is to use it.
4
Auxiliary Power Source.
Hardwired to 0.
3
PME Clock.
Hardwired to 0 to indicate GMCH2-M does not support PME# generation.
2:0
Version.
Hardwired to 010b to indicate there are 4 bytes of power management registers
implemented and that this device complies with revision 1.1 of the
PCI Power Management Interface
Specification
.
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