參數(shù)資料
型號(hào)： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 131/163頁
文件大?。?/td> 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
Datasheet
131
4.9.3.
SDRAMT Register Programming
Several DRAM timing parameters are programmable in the GMCH2-M configuration registers. Table 18
summarizes the programmable parameters.
Table 17. Programmable SDRAM Timing Parameters
Parameter
DRAMT Bit
Values (SCLKs)
RAS# Precharge (SRP)
0
2,3
RAS# to CAS# Delay (SRCD)
1
2,3
CAS# Latency (CL)
2
2,3
DRAM Cycle Time (DCT)
4
Tras = 5,6
Trc = 7,8
These parameters are controlled via the DRAMT register. In order to support different device speed
grades, CAS# Latency, RAS# to CAS# Delay, and RAS# Precharge are all programmable as either two
or three SCLKs. To provide flexibility, these are each controlled by separate register bits. That is, the
GMCH2-M can support any combination of CAS# Latency, RAS# to CAS# Delay and RAS# Precharge.
4.9.4.
SDRAM Paging Policy
The GMCH2-M can maintain up to 4 active pages in any one row; however, the GMCH2-M does not
support active pages in more than 1 row at a time.
The DRAM page closing policy (DPCP) in the GMCH2-M configuration register (GMCHCFG) controls
the page closing policy of the. This bit controls whether the GMCH2-M will precharge bank or
precharge all during the service of a page miss. When this bit is set to 0, the GMCH2-M will prechange
bank during the service of a page miss. When this bit is set to 1, the GMCH2-M will prechange all during
the service of a page miss.
4.10.
Intel Dynamic Video Memory Technology (D.V.M.T.)
The internal graphics device on the GMCH2-M supports Intel Dynamic Video Memory Technology
(D.V.M.T.). Intel
D.V.M.T. dynamically responds to application requirements by allocating the proper
amount of display and texturing memory. For more details please refer to the document entitled, “Intel
810 chipset: Great Performance for Value PCs” available at: http://deverlolper.intel.com/design/
chipsets/ 810/810white.htm.
In addition to Intel
D.V.M.T., the GMCH2-M supports Display Cache (DC). The graphics engine of the
GMCH2-M uses DC for implementing rendering buffers (e.g., Z buffers). This rendering model requires
4 MB of display cache and allows graphics rendering (performed across the graphics display cache bus)
and texture MIP map access (performed across the system memory bus) simultaneously. In using Intel
D.V.M.T., all graphics rendering is implemented in system memory. The system memory bus is
arbitrated between texture MIP-map accesses and rendering functions.
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