參數(shù)資料
型號： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 98/163頁
文件大?。?/td> 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
98
Datasheet
3.8.2.
DID2—Device Identification Register (Device 2)
Address Offset:
02h
03h
Default Value:
1132h
Attribute:
Read Only
This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI device.
Writes to this register have no effect.
Bit
Description
15:0
Device Identification Number.
This is a 16 bit value assigned to the internal graphics device of the
GMCH2-M.
1132h = Device ID for Device 2.
3.8.3.
PCICMD2—PCI Command Register (Device 2)
Address Offset:
04h
05h
Default:
0004h
Access:
Read Only, Read/Write
This 16-bit register provides basic control over the GMCH2-M's ability to respond to PCI cycles. The
PCICMD Register in GMCH2-M disables GMCH2-M PCI compliant master accesses to main memory.
15
10
9
8
Reserved (0)
FB2B
(HW=0)
SERR En
(HW=0)
7
6
5
4
3
2
1
0
Addr/Data
Stepping
(HW=0)
Parity
Error En
(HW=0)
VGA Pal
Sn
(HW=0)
Mem WR
& Inval En
(HW=0)
Special
Cycle En
(HW=0)
Bus
Master En
Mem Acc
En
I/O Acc En
Bits
Description
15:10
Reserved
.
9
Fast Back-to-Back (FB2B)
RO.
(Not Implemented). Hardwired to 0.
8
SERR# Enable (SERRE)
RO.
(Not Implemented). Hardwired to 0.
7
Address/Data Stepping
RO.
(Not Implemented). Hardwired to 0.
6
Parity Error Enable (PERRE)
the category of devices that does not corrupt programs or data in system memory or hard drives,
GMCH2-M ignores any parity error that it detects and continues with normal operation.
RO.
(Not Implemented). Hardwired to 0. Since GMCH2-M belongs to
5
Video Palette Snooping (VPS)
RO.
This bi is hardwired to 0 to disable snooping.
4
Memory Write and Invalidate Enable (MWIE)
memory write and invalidate commands.
RO.
Hardwired to 0. GMCH2-M does not support
3
Special Cycle Enable (SCE)
RO.
This bit is hardwired to 0. GMCH2-M ignores Special cycles.
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