參數(shù)資料
型號： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 19/163頁
文件大?。?/td> 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
Datasheet
19
2.
Signal Description
This section provides a detailed description of the Intel
815EM chipset GMCH2-M signals. The signals
are arranged in functional groups according to their associated interface. The states of all of the signals
during reset are provided in the System Reset section.
The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when the
signal is at a low voltage level. When “#” is not present after the signal name the signal is asserted when
at the high voltage level.
The following notations are used to describe the signal type:
I
Input pin
O
Output pin
I/OD
Input / Open Drain Output pin. This pin requires a pullup 3.3V.
I/O
Bi-directional Input/Output pin
s/t/s
Sustained Tristate. This pin is driven to its inactive state prior to tri-stating.
as/t/s
Active Sustained Tristate. This applies to some of the hub interface signals. This
pin is weakly driven to its last driven value.
The signal description also includes the type of buffer used for the particular signal:
GTL+
Open Drain GTL+ interface signal. Refer to the GTL+ I/O Specification for
complete details. These signals will be actively driven high for a short period of
time to assist timing when the Intel
815EM chipset is configured for 100-MHz
Host interface. GTL+ signals are inverted bus signals where a low voltage
represents a logical “1”.
AGP
AGP interface signals. These signals can be programmed to be compatible with
AGP 2.0 3.3V or 1.5V Signaling Environment DC and AC Specifications. In
3.3V mode the buffers are not 5V tolerant. In 1.5V mode the buffers are not
3.3V tolerant.
CMOS
The CMOS buffers are Low Voltage TTL compatible signals. These are 3.3V
only.
LVTTL
Low Voltage TTL compatible signals. There are 3.3V only.
1.8V
1.8V signals for the digital video interface
Analog
Analog CRT Signals
Note:
That the processor address and data bus signals (Host Interface) are logically inverted signals (i.e., the
actual values are inverted of what appears on the processor bus). This must be taken into account and the
addresses and data bus signals must be inverted inside the Intel
815EM chipset GMCH2-M. All
processor control signals follow normal convention. A 0 indicates an active level (low voltage) if the
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