參數(shù)資料
型號(hào)： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 151/163頁
文件大?。?/td> 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
Datasheet
151
When the system resumes from POS, ICH2-M can optionally resume without resetting the system, can
reset the processor only, or can reset the entire system. When no reset is performed, the ICH2-M only
needs to wait for the clock synthesizer and processor PLLs to lock before the system is resumed. This
takes typically 20ms.
4.18.6.
Suspend-to-RAM (STR) (S3 State)
S3 state is also called STR, suspend to RAM state. Power is removed from most of the system
components during STR, except the DRAM. Power is supplied to the host bridge (for DRAM Suspend
Refresh) and RTC. ICH2-M provides control signals and 32 kHz Suspend Clock (SUSCLK) to allow for
DRAM refresh and to turn off the clock synthesizer and other power planes. ICH2-M will reset the
system on resume from STR.
4.18.7.
Suspend to DISK (STD) S4 State
Power is removed from most of the system components during STD. Power is maintained to the RTC
and Suspend Well logic in the ICH2-M. ICH2-M will reset the system on resume from STD. This state
can also be called the Soft Off (SOFF) state. The difference depends on whether the system state is
restored by software to a pre-suspend condition or if the system is rebooted.
4.18.8.
Graphics Controller Requirements
PC9x implies that D0 and D3 are obligatory for graphics controllers. D0, D2, and D3 are obligatory for
monitors. Intel
815EM chipset also permits D1 for monitors. Intel
815EM chipset does not implement
a D1 graphics controller state.
4.18.8.1.
The D0 State
This is the normal on state for the Intel
815EM chipset graphics functions. The Intel
815EM chipset
graphics functions enter this state after initialization by the Video BIOS.
4.18.8.2.
The D3 State
During D3, graphics configuration space must remain accessible when power is on, but memory and I/O
space access are disabled. During D3, the driver has turned off the DAC and Intel
815EM chipset does
not pulse
HSYNC
and
VSYNC
in this state.
When the OS decides to put the Intel
815EM chipset graphics functions into D3, it calls the Intel
815EM chipset graphics driver and tells it to place the device into the D3 state. The driver saves the
device context. Device context consists of the Intel
815EM chipset graphics mode as well as local and
non-local video memory context.
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