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參數(shù)資料
| 型號： | 82815EM |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 41/163頁 |
| 文件大?。?/td> | 1049K |
| 代理商： | 82815EM |
Intel
82815EM GMCH
R
Datasheet
41
Table 4. GMCH2-M PCI Configuration Space (Device #0)
Address
Offset
Register
Symbol
Register Name
Default Value
Access
00–01h
VID
Vendor Identification
8086h
RO
02–03h
DID
Device Identification (Device 0)
1130h
RO
04–05h
PCICMD
PCI Command Register
0006h
Read/Write
06–07h
PCISTS
PCI Status Register
0090h
Read/Write
,
RO
08h
RID (A0)
Revision Identification for A0-step
10h
RO
08h
RID (A1)
Revision Identification for A1-step
11h
RO
09h
Reserved
0Ah
SUBC
Sub-Class Code
00h
RO
0Bh
BCC
Base Class Code
06h
RO
0Ch
Reserved
0Dh
MLT
Master Latency Timer
00h
RO
0Eh
HDR
Header Type
00h
RO
0Fh
Reserved
10-13h
APBASE
Aperture Base Configuration
00000008h
(AGP)
00000000h (GFX)
Read/Write
,
RO
14-2Bh
Reserved
2C–2Dh
SVID
Subsystem Vendor Identification
0000h
Read/Write
2E–2Fh
SID
Subsystem Identification
0000h
Read/Write
30–33h
Reserved
34h
CAPPTR
Capabilities Pointer
88h
RO
35–4Fh
Reserved
50h
GMCHCFG
GMCH2-M Configuration
01ss 0s00b
Read/Write
51h
APCONT
Aperture Control
00h
Read/Write
,
RO
52h
DRP
DRAM Row Population
00h
Read/Write
53h
DRAMT
DRAM Timing Register
00h
Read/Write
54h
DRP2
DRAM Row Population Register 2
00h
Read/Write
55–57h
Reserved
58h
FDHC
Fixed DRAM Hole Control
00h
Read/Write
59-5Fh
PAM
Programmable Attributes Map
00h
Read/Write
60h
C3STAT
C3 control and status
00h
Read/Write
,
RO
61–6Fh
Reserved
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