參數(shù)資料
型號: 82815EM
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù): 76/163頁
文件大小: 1049K
代理商: 82815EM
Intel
82815EM GMCH
R
76
Datasheet
3.6.34.
LPTT—AGP Low Priority Transaction Timer Register (Device 0)
Address Offset:
BDh
Default Value:
00h
Access:
Read/Write
Size:
8 bits
LPTT is an 8-bit register similar in a function to AMTT. This register is used to control the minimum
tenure on the AGP for low priority data transaction (both reads and writes) issued using PIPE# or SB
mechanisms. The number of clocks programmed in the LPTT represents the guaranteed time slice
(measured in 66MHz clocks) allotted to the current low priority AGP transaction data transfer state. This
does not necessarily apply to a single transaction but it can span over multiple low-priority transactions
of the same type. After this time expires the AGP arbiter may grant the bus to another agent if there is a
pending request. The LPTT does not apply in the case of high-priority request where ownership is
transferred directly to high-priority requesting queue. The default value of LPTT is 00h and disables this
function. The LPTT value can be programmed with 8 clock granularity. For example, if the LPTT is
programmed to 10h, then the selected value corresponds to the time period of 16 AGP (66-MHz) clocks.
(AGP mode only.)
7
3
2
0
Low Priority Transaction Timer Count Value
Reserved
Bit
Description
7:3
Low Priority Transaction Timer Count Value.
The number of clocks programmed in these bits
represents the guaranteed time slice (measured in eight 66MHz clock granularity) allotted to the current
low priority AGP transaction data transfer state.
2:0
Reserved.
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