- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366260 > 82815EM Controller Miscellaneous - Datasheet Reference PDF資料下載
參數(shù)資料
| 型號： | 82815EM |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 122/163頁 |
| 文件大?。?/td> | 1049K |
| 代理商： | 82815EM |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁當(dāng)前第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁
Intel
82815EM GMCH
R
122
Datasheet
The GMCH2-M accepts accesses from the hub interface to the following address ranges:
All memory Read/Write accesses to Main DRAM including PAM region (except SMM space)
All memory Read/Write accesses to the Graphics Aperture defined by APBASE and APSIZE.
All Hub interface memory write accesses to AGP memory range defined by MBASE, MLIMIT,
PMBASE, and PMLIMIT.
Memory writes to VGA range on AGP if enabled.
The hub interface memory accesses that fall elsewhere within the memory range are considered invalid
and will be remapped to a translated memory address, snooped on the host bus, and dispatched to
DRAM. Reads will return all 1’s with Master Abort completion. Writes will have BE’s deasserted and
will terminate with Master Abort if completion is required. I/O cycles will not be accepted. They are
terminated with Master Abort completion packets.
4.7.2.
The Hub Interface Accesses to GMCH2-M that Cross Device
Boundaries
The Hub interface accesses are limited to 256 bytes but have no restrictions on crossing address
boundaries. A single hub interface request may therefore span device boundaries (AGP, DRAM) or cross
from valid addresses to invalid addresses (or visa versa). The GMCH2-M does not support transactions
that cross device boundaries. For reads and for writes requiring completion, the GMCH2-M will provide
separate completion status for each naturally-aligned 32 or 64 byte block. If the starting address of a
transaction hits a valid address the portion of a request that hits that target device (AGP or DRAM) will
complete normally.
The remaining portion of the access that crosses a device boundary (targets a different device than that of
the starting address) or hits an invalid address will be remapped to memory address 0h, snooped on the
host bus, and dispatched to DRAM. Reads will return all 1’s with Master Abort completion. Writes will
have BE’s deasserted and will terminate with Master Abort if completion is required.
If the starting address of a transaction hits a invalid address the entire transaction will be remapped to
memory address 0h, snooped on the host bus, and dispatched to DRAM. Reads will return all 1’s with
Master Abort completion. Writes will have BE’s deasserted and will terminate with Master Abort if
completion is required.
4.7.3.
AGP Interface Decode Rules
4.7.3.1.
Cycles Initiated Using PCI Protocol
The GMCH2-M does not support any AGP/PCI access targeting the hub interface. The GMCH2-M will
claim AGP/PCI initiated memory read and write transactions decoded to the main DRAM range or the
Graphics Aperture range. All other memory read and write requests will be master-aborted by the
AGP/PCI initiator as a consequence of GMCH2-M not responding to a transaction.
Under certain conditions, the GMCH2-M restricts access to the DOS Compatibility ranges governed by
the PAM registers by distinguishing access type and destination bus. The GMCH2-M accepts AGP/PCI
write transactions to the compatibility ranges if the PAM designates DRAM as write-able. If accesses to
a range are not write enabled by the PAM, the GMCH2-M does not respond and the cycle will result in a
master-abort. AGP/PCI read transactions to the compatibility ranges are accepted if the PAM designates
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 82820 | Interface IC |
| 82830009 | MOTOR 12VDC 2100RPM |
| 82830010 | MOTOR 24VDC 2100RPM |
| 82830MP | Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M) |
| 82840 | Interface IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82-816-1000 | 功能描述:RF 連接器 ST Plug RG-108A 50 Ohm RoHS:否 制造商:Bomar Interconnect 產(chǎn)品:Connectors 射頻系列:BNC 型式:Jack (Female) 極性: 觸點(diǎn)電鍍:Gold 阻抗: 端接類型:Solder 主體類型:Straight Bulkhead 電纜類型: |
| 82-81641 | 制造商:CHOMERICS (PARKER) 功能描述: |
| 828168-1 | 制造商:TE Connectivity 功能描述:7P MT RV100 CONNECTOR |
| 828168-2 | 功能描述:7P MT TAND BU STECK RoHS:是 類別:連接器，互連式 >> 矩形 - 自由懸掛，面板安裝 系列:AMPMODU RV 100 RoHS指令信息:5-643816-8 Statement of Compliance 3D 型號:5-643816-8.pdf 標(biāo)準(zhǔn)包裝:500 系列:MTA-100 連接器類型:插座 觸點(diǎn)類型：:母形插口 位置數(shù):28 間距:0.100"（2.54mm） 行數(shù):1 行間距:- 安裝類型:自由懸掛 緊固型:鎖銷滑道 電纜端接:IDC 導(dǎo)線類型:離散式或帶狀纜線 線規(guī):28 AWG 特點(diǎn):閉端，帶電極標(biāo)記 觸點(diǎn)表面涂層:錫 觸點(diǎn)涂層厚度:80µin（2.03µm） 顏色:綠 包裝:散裝 相關(guān)產(chǎn)品:A1998-ND - HEAD ASSEM TOOL FOR MTA-100 RECP |
| 828169-1 | 功能描述:集管和線殼 2X7P MT TAND SOCKET CONNECTOR RoHS:否 產(chǎn)品種類:1.0MM Rectangular Connectors 產(chǎn)品類型:Headers - Pin Strip 系列:DF50 觸點(diǎn)類型:Pin (Male) 節(jié)距:1 mm 位置/觸點(diǎn)數(shù)量:16 排數(shù):1 安裝風(fēng)格:SMD/SMT 安裝角:Right 端接類型:Solder 外殼材料:Liquid Crystal Polymer (LCP) 觸點(diǎn)材料:Brass 觸點(diǎn)電鍍:Gold 制造商:Hirose Connector |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。