參數(shù)資料
型號： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 20/163頁
文件大小： 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
20
Datasheet
signal is followed by # symbol and a 1 indicates an active level (high voltage) if the signal has no #
suffix.
The following table shows the Vtt/Vdd and Vref levels for the various interfaces:
Table 2. Voltage Levels for Each Interface
Interface
Vtt/Vdd
(nominal)
Vref
GTL+
1.5v
2/3 * Vtt
AGP
1.5v
3.3v
1.5v: 0.5 * Vagpdd
3.3v: 0.4 * Vagpdd
Hub Interface
1.8v
0.5 * Vdd
2.1.
Host Interface Signals
Signal Name
Type
Description
CPURST#
O
GTL+
CPU Reset:
The GMCH2-M asserts CPURST# while RESET# (PCIRST# from
ICH2-M) is asserted and for approximately 1ms after RESET# is deasserted. The
GMCH2-M also pulses CPURST# for approximately 1ms when requested via a hub
interface special cycle. The CPURST# allows the processor to begin execution in a
known state.
HA [31:3]#
I/O
GTL+
Host Address Bus:
HA[31:3]# connect to the processor address bus. During
processor cycles, HA[31:3]# are inputs. The GMCH2-M drives HA[31:3]# during
snoop cycles on behalf of Primary PCI. Note that the address bus is inverted on the
processor bus.
A low value on HA[15]# sampled at the rising edge of CPURST# informs the
processor to support Quick-Start stop clock mode. If HA[15]# is sampled high at
CPURST# rising edge, it informs the processor to support Stop-Grant mode.
HD [63:0]#
I/O
GTL+
Host Data:
These signals are connected to the processor data bus. Note that the
data signals are inverted on the processor bus.
ADS#
I/O
GTL+
Address Strobe:
The processor bus owner asserts ADS# to indicate the first of two
cycles of a
request phase
.
BNR#
I/O
GTL+
Block Next Request:
Used to block the current request bus owner from issuing a
new request. This signal is used to dynamically control the processor bus pipeline
depth.
BPRI#
O
GTL+
Priority Agent Bus Request:
The GMCH2-M is the only Priority Agent on the
processor bus. It asserts this signal to obtain the ownership of the address bus.
This signal has priority over symmetric bus requests and will cause the current
symmetric owner to stop issuing new transactions unless the HLOCK# signal was
asserted.
DBSY#
I/O
GTL+
Data Bus Busy:
Used by the data bus owner to hold the data bus for transfers
requiring more than one cycle.
DEFER#
O
GTL+
Defer:
The GMCH2-M will generate a deferred response as defined by the rules of
the GMCH2-M dynamic defer policy. The GMCH2-M will also use the DEFER#
signal to indicate a processor retry response.
DRDY#
I/O
GTL+
Data Ready:
Asserted for each cycle that data is transferred.
相關PDF資料
PDF描述
82820 Interface IC
82830009 MOTOR 12VDC 2100RPM
82830010 MOTOR 24VDC 2100RPM
82830MP Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)
82840 Interface IC
相關代理商/技術參數(shù)
參數(shù)描述
82-816-1000 功能描述:RF 連接器 ST Plug RG-108A 50 Ohm RoHS:否 制造商:Bomar Interconnect 產(chǎn)品:Connectors 射頻系列:BNC 型式:Jack (Female) 極性: 觸點電鍍:Gold 阻抗: 端接類型:Solder 主體類型:Straight Bulkhead 電纜類型:
82-81641 制造商:CHOMERICS (PARKER) 功能描述:
828168-1 制造商:TE Connectivity 功能描述:7P MT RV100 CONNECTOR
828168-2 功能描述:7P MT TAND BU STECK RoHS:是 類別:連接器，互連式 >> 矩形 - 自由懸掛，面板安裝 系列:AMPMODU RV 100 RoHS指令信息:5-643816-8 Statement of Compliance 3D 型號:5-643816-8.pdf 標準包裝:500 系列:MTA-100 連接器類型:插座 觸點類型：:母形插口 位置數(shù):28 間距:0.100"（2.54mm） 行數(shù):1 行間距:- 安裝類型:自由懸掛 緊固型:鎖銷滑道 電纜端接:IDC 導線類型:離散式或帶狀纜線 線規(guī):28 AWG 特點:閉端，帶電極標記 觸點表面涂層:錫 觸點涂層厚度:80µin（2.03µm） 顏色:綠 包裝:散裝 相關產(chǎn)品:A1998-ND - HEAD ASSEM TOOL FOR MTA-100 RECP
828169-1 功能描述:集管和線殼 2X7P MT TAND SOCKET CONNECTOR RoHS:否 產(chǎn)品種類:1.0MM Rectangular Connectors 產(chǎn)品類型:Headers - Pin Strip 系列:DF50 觸點類型:Pin (Male) 節(jié)距:1 mm 位置/觸點數(shù)量:16 排數(shù):1 安裝風格:SMD/SMT 安裝角:Right 端接類型:Solder 外殼材料:Liquid Crystal Polymer (LCP) 觸點材料:Brass 觸點電鍍:Gold 制造商:Hirose Connector
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*