Intel
82815EM GMCH
R
4
Datasheet
3.5.1.
3.5.2.
3.5.3.
Host-Hub Interface Bridge/DRAM Controller Device Registers (Device #0) .................40
3.6.1.
VID—Vendor Identification Register (Device 0)...........................................43
3.6.2.
DID—Device Identification Register (Device 0)...........................................43
3.6.3.
PCICMD—PCI Command Register (Device 0) ...........................................44
3.6.4.
PCISTS—PCI Status Register (Device 0)...................................................45
3.6.5.
RID—Revision Identification Register (Device 0) ........................................46
3.6.6.
SUBC—Sub-Class Code Register (Device 0).............................................46
3.6.7.
BCC—Base Class Code Register (Device 0)..............................................46
3.6.8.
MLT—Master Latency Timer Register (Device 0) .......................................47
3.6.9.
HDR—Header Type Register (Device 0).....................................................47
3.6.10.
APBASE—Aperture Base Configuration Register (Device 0 - AGP MODE
ONLY)
.....................................................................................................................48
3.6.11.
SVID—Subsystem Vendor Identification Register (Device 0) .....................49
3.6.12.
SID—Subsystem Identification Register (Device 0) ....................................49
3.6.13.
CAPPTR—Capabilities Pointer (Device 0) ..................................................50
3.6.14.
GMCHCFG—GMCH2-M Configuration Register (Device 0).......................50
3.6.15.
APCONT—Aperture Control (Device 0) ......................................................52
3.6.16.
DRP—DRAM Row Population Register (Device 0).....................................53
3.6.17.
DRAMT—DRAM Timing Register (Device 0)..............................................54
3.6.18.
DRP2—DRAM Row Population Register 2 (Device 0)................................55
3.6.19.
FDHC
Fixed DRAM Hole Control Register (Device 0)............................56
3.6.20.
PAM
Programmable Attributes Map Registers (Device 0)........................56
3.6.21.
C3STATUS —C3 Control and Status Register (Device #0)........................59
3.6.22.
SMRAM - System Management RAM Control Register (Device 0).............60
3.6.23.
MISCC—Miscellaneous Control Register (Device 0) ..................................62
3.6.24.
CAPID—Capability Identification (Device 0 - AGP MODE ONLY)...............63
3.6.25.
BUFF_SC—System Memory Buffer Strength Control Register (Device 0).65
3.6.26.
BUFF_SC2-System Memory Buffer Strength Control Register 2 (Device 0)68
3.6.27.
ACAPID—AGP Capability Identifier Register (Device 0).............................69
3.6.28.
AGPSTAT—AGP Status Register (Device 0)..............................................70
3.6.29.
AGPCMD—AGP Command Register (Device 0) ........................................71
3.6.30.
AGPCTRL—AGP Control Register (Device 0)............................................72
3.6.31.
APSIZE—Aperture Size (Device 0) .............................................................73
3.6.32.
ATTBASE-Aperture Translation Table Base Register (Device 0) ...............74
3.6.33.
AMTT—AGP Multi-Transaction Timer (Device 0) .......................................75
3.6.34.
LPTT—AGP Low Priority Transaction Timer Register (Device 0)...............76
3.6.35.
GMCHCFG—GMCH2-M Configuration Register (Device 0).......................77
3.6.36.
ERRCMD—Error Command Register (Device 0)........................................78
AGP/PCI Bridge Registers – (Device #1 - Visible in AGP Mode Only)..........................79
3.7.1.
VID1—Vendor Identification Register (Device 1).........................................80
3.7.2.
DID1—Device Identification Register (Device 1).........................................80
3.7.3.
PCICMD1—PCI-PCI Command Register (Device 1) ..................................81
3.7.4.
PCISTS1—PCI-PCI Status Register (Device 1)..........................................82
3.7.5.
RID1—Revision Identification Register (Device 1) ......................................83
3.7.6.
SUBC1—Sub-Class Code Register (Device 1)...........................................83
3.7.7.
BCC1—Base Class Code Register (Device 1)............................................84
3.7.8.
MLT1—Master Latency Timer Register (Device 1) .....................................84
3.7.9.
HDR1—Header Type Register (Device 1)...................................................84
3.7.10.
PBUSN—Primary Bus Number Register (Device 1)....................................85
3.7.11.
SBUSN—Secondary Bus Number Register (Device 1)...............................85
3.7.12.
SUBUSN—Subordinate Bus Number Register (Device 1)..........................85
Logical PCI Bus #0 Configuration Mechanism ............................................40
Primary PCI (PCI0) and Downstream Configuration Mechanism................40
Internal Graphics Device (GFX) Configuration Mechanism.........................40
3.6.
3.7.