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參數(shù)資料
| 型號： | 82815EM |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 121/163頁 |
| 文件大?。?/td> | 1049K |
| 代理商： | 82815EM |
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Intel
82815EM GMCH
R
Datasheet
121
The I/O accesses, other than ones used for PCI configuration space access or ones that target the internal
Graphics Device (GFX) (or AGP/PCI) are forwarded to the hub interface. The GMCH2-M will not post
I/O write cycles to IDE. The PCICMD1 or PCICMD2 register can disable the routing of I/O cycles to
the AGP. The GMCH2-M never responds to I/O cycles initiated on AGP.
4.6.1.
AGP/PCI - I/O Address Mapping
The GMCH2-M can be programmed to direct non-memory (I/O) accesses to the AGP bus interface when
processor initiated I/O cycle addresses are within the AGP I/O address range. This range is controlled
via the I/O Base Address (IOBASE) and I/O Limit Address (IOLIMIT) registers in GMCH2-M Device
#1 configuration space.
Address decoding for this range is based on the following concept. The top 4 bits of the respective I/O
Base and I/O Limit registers correspond to address bits A[15:12] of an I/O address. For the purpose of
address decoding, the GMCH2-M assumes that lower 12 address bits A[11:0] of the I/O base are zero
and that address bits A[11:0] of the I/O limit address are FFFh. This forces the I/O address range
alignment to 4KB boundary and produces a size granularity of 4KB. The GMCH2-M positively decodes
I/O accesses to AGP I/O address space as defined by the following equation:
I/O_Base_Address
≤
processor I/O Cycle Address
≤
I/O_Limit_Address
The plug-and-play configuration software programs the effective size of the range and it depends on the
size of I/O space claimed by the AGP device.
The GMCH2-M also forwards accesses to the Legacy VGA I/O ranges according to the settings of
Device #1 configuration registers BCTRL (VGA Enable) and PCICMD1 (IOAE1), unless a second
adapter (monochrome) is present on the hub interface/PCI (or ISA). The MDAP configuration bit
determines the presence of a second graphics adapter. When MDAP is set, the MCH will decode legacy
monochrome IO ranges and forward them to the hub interface. The IO ranges decoded for the
monochrome adapter are 3B4h, 3B5h, 3B8h, 3B9h, 3Bah and 3BFh. The PCICMD1 register can disable
the routing of I/O cycles to the AGP.
Note that the GMCH2-M Device #1 I/O address range registers defined above are used for all I/O space
allocation for any devices requiring such a window on AGP. These devices would include the AGP
device, PCI-66MHz/3.3V agents, and multifunctional AGP devices where one or more functions are
implemented as PCI devices.
4.7.
GMCH2-M Address Decode Rules and Cross-Bridge
Address Mapping
The GMCH2-M’s address map applies globally to accesses arriving on any of the three interfaces (i.e.,
Host bus, hub interface or from the internal Graphics Device).
4.7.1.
Address Decode Rules
The GMCH2-M accepts all memory Read and Write accesses from the hub interface to both System
Memory and Graphics Memory. The hub interface accesses that fall elsewhere within the PCI memory
range will not be accepted. The GMCH2-M never responds to hub interface initiated I/O read or write
cycles.
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