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| 型號： | 82815EM |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 35/163頁 |
| 文件大小： | 1049K |
| 代理商： | 82815EM |
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Intel
82815EM GMCH
R
Datasheet
35
3.
PCI Configuration Registers
This section describes the PCI Configuration Register set.
The GMCH2-M contains PCI configuration registers for Device 0 (Host-hub interface Bridge/DRAM
Controller), Device 1 (AGP Bridge), and Device 2 (GMCH2-M internal graphics device).
The GMCH2-M also contains an extensive set of registers and instructions for controlling its graphics
operations. Intel
graphics drivers provide the software interface at this architectural level. The
register/instruction interface is transparent at the Application Programmers Interface (API) level and
thus, beyond the scope of this document.
3.1.
Register Nomenclature and Access Attributes
RO
Read Only
. If a register is read only, writes to this register have no effect.
R/w
Read/Write
. A register with this attribute can be read and written
R/WC
Read/Write Clear
. A register bit with this attribute can be read and written. However, a write of a
1 clears (sets to 0) the corresponding bit and a write of a 0 has no effect.
R/WO
Read/Write Once
. A register bit with this attribute can be written to only once after power up.
After the first write, the bit becomes read only.
Reserved
Bits
Some of the GMCH2-M registers described in this section contain reserved bits. These bits are
labeled "Reserved” or “Intel
Reserved”. Software must deal correctly with fields that are
reserved. On reads, software must use appropriate masks to extract the defined bits and not rely
on reserved bits being any particular value. On writes, software must ensure that the values of
reserved bit positions
are preserved. That is, the values of reserved bit positions must first be
read, merged with the new values for other bit positions and then written back. Note the software
does not need to perform read, merge, write operation for the configuration address register.
Reserved
Registers
In addition to reserved bits within a register, the GMCH2-M contains address locations in the
configuration space of the Host-hub interface Bridge/DRAM Controller and the internal graphics
device entities that are marked either "Reserved” or Intel
Reserved”. When a “Reserved”
register location is read, a random value can be returned. (“Reserved” registers can be 8-, 16-, or
32-bit in size). Registers that are marked as “Reserved” must not be modified by system
software. Writes to “Reserved” registers may cause system failure.
Default
Value Upon
Reset
Upon a Full Reset, the GMCH2-M sets all of its internal configuration registers to predetermined
default
states. Some register values at reset are determined by external strapping options. The
default state represents the minimum functionality feature set required to successfully bring up
the system. Hence, it does not represent the optimal system configuration. It is the responsibility
of the system initialization software (usually BIOS) to properly determine the DRAM
configurations, operating parameters and optional system features that are applicable, and to
program the GMCH2-M registers accordingly.
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