參數(shù)資料
型號: 82815EM
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù): 81/163頁
文件大小: 1049K
代理商: 82815EM
Intel
82815EM GMCH
R
Datasheet
81
3.7.3.
PCICMD1—PCI-PCI Command Register (Device 1)
Address Offset:
04-05h
Default:
0000h
Access:
Read/Write, Read Only
Size
16 bits
15
10
9
8
Reserved (0)
FB2B
(Not Impl)
SERR En
7
6
5
4
3
2
1
0
Addr/Data
Stepping
(Not Impl)
Parity
Error En
(Not Impl)
Reserved
Mem WR
& Inval En
Special
Cycle En
Bus
Master En
Mem Acc
En
I/O Acc En
Bit
Descriptions
15:10
Reserved
.
9
Fast Back-to-Back: Not Applicable-hardwired to “0”.
8
SERR Message Enable (SERRE1)
. This bit is a global enable bit for Device 1 SERR messaging. The
GMCH2-M does not have an SERR# signal. The GMCH2-M communicates the SERR# condition by
sending an SERR message to the ICH2-M.
0 = the SERR message is not generated by the GMCH2-M for Device 1
1 = the GMCH2-M is enabled to generate SERR messages over hub interface for specific Device 1
error conditions that are individually enabled in the ERRCMD1 and BCTRL registers. The error status is
reported in the PCISTS1 register.
NOTE: This bit only controls SERR messaging for the Device 1. Device 0 has its own SERRE bit
to control error reporting for error conditions occurring on Device 0. The two control bits are
used in a logical OR manner to enable the SERR hub interface message mechanism.
7
Address/Data Stepping: Not applicable. Hardwired to “0”.
6
Parity Error Enable (PERRE1):
PERR# is not supported on AGP/PCI1.
Hardwired to “0”.
5
Reserved.
4
Memory Write and Invalidate Enable: (RO)
This bit is implemented as RO and returns a value of “0”
when read.
3
Special Cycle Enable: (RO)
This bit is implemented as Read Only and returns a value of “0” when
read.
2
Bus Master Enable (BME1): (Read/Write)
0 =(default) AGP Master initiated FRAME# cycles will be ignored by the GMCH2-M resulting in a
Master Abort. Ignoring incoming cycles on the secondary side of the P2P bridge effectively disables the
bus master on the primary side.
1 = AGP Master initiated FRAME# cycles will be accepted by the GMCH2-M if they hit a valid address
decode range. This bit has no affect on AGP Master originated SBA or PIPE# cycles.
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