參數(shù)資料
型號： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 56/163頁
文件大?。?/td> 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
56
Datasheet
3.6.19.
FDHC
Address Offset:
Default Value:
Access:
Size:
Fixed DRAM Hole Control Register (Device 0)
58h
00h
Read/Write
8 bits
This 8-bit register controls a single fixed DRAM hole: 15-16 MB.
7
6
0
Hole EN
Reserved
Bit
Description
7
Hole Enable (HEN).
This field enables a memory hole in DRAM space.
Host cycles matching an enabled hole are passed on to ICH through the hub interface. Hub interface
and PCI cycles matching an enabled hole will be ignored by the GMCH2-M. Note that a selected hole is
not re-mapped.
0 = No Hole Enabled
1 = 15 MB-16 MB (1MB) Hole Enabled
6:0
Reserved.
3.6.20.
PAM
Address Offset:
Default Value:
Attribute:
Size:
Programmable Attributes Map Registers (Device 0)
59 - 5Fh
00h
Read/Write
4 bits/register
The GMCH2-M allows programmable memory attributes on 13
Legacy
memory segments of various
sizes in the 768 KB to 1 MB address range. Seven Programmable Attribute Map (PAM) Registers are
used to support these features. Cacheability of these areas is controlled via the MTRR registers in the
mobile Intel
Pentium
III
processor. Two bits are used to specify memory attributes for each memory
segment. These bits apply to both host, AGP/PCI and hub interface initiator accesses to the PAM areas.
These attributes are:
RE - Read Enable. When RE = 1, the processor read accesses to the corresponding memory segment
are claimed by the GMCH2-M and directed to main memory. Conversely, when RE = 0, the host
read accesses are directed to the hub interface/PCI0.
WE - Write Enable. When WE = 1, the host write accesses to the corresponding memory segment
are claimed by the GMCH2-M and directed to main memory. Conversely, when WE = 0, the host
write accesses are directed to the hub interface/PCI0.
The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write, or
disabled. For example, if a memory segment has RE = 1 and WE = 0, the segment is Read Only.
Each PAM Register controls two regions, typically 16 KB in size. Each of these regions has a 4-bit field.
The four bits that control each region have the same encoding and are defined in the following table.
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