參數(shù)資料
型號： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 79/163頁
文件大?。?/td> 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
Datasheet
79
Bit
Description
0
SERR on Access to Invalid Graphics Aperture Translation Table Entry.
0 = reporting of this condition via SERR messaging is disabled.When this bit is set to “
1 = the GMCH2-M generates an SERR hub interface special cycle when an invalid translation table
entry was returned in response to a AGP access to the graphics aperture.
3.7.
AGP/PCI Bridge Registers – (Device #1 - Visible in AGP
Mode Only)
These registers are accessible through the configuration mechanism defined in an earlier section of this
document.
Table 8. GMCH2-M Configuration Space (Device #1)
Address
Offset
Register
Symbol
Register Name
Default Value
Access Type
00-01h
VID1
Vendor Identification
8086h
RO
02-03h
DID1
Device Identification
1131h
RO
04-05h
PCICMD1
PCI Command Register
0000h
RO, Read/Write
06-07h
PCISTS1
PCI Status Register
0020h
RO, Read/WriteC
08h
RID1 (A0)
Revision Identification for A0-step
10h
RO
08h
RID1 (A1)
Revision Identification for A1-step
11h
RO
09
Reserved
00h
0Ah
SUBC1
Sub-Class Code
04h
RO
0Bh
BCC1
Base Class Code
06h
RO
0Ch
Reserved
00h
0Dh
MLT1
Master Latency Timer
00h
Read/Write
0Eh
HDR1
Header Type
01h
RO
0F-17h
Reserved
00h
18h
PBUSN
Primary Bus Number
00h
RO
19h
SBUSN
Secondary Bus Number
00h
Read/Write
1Ah
SUBUSN
Subordinate Bus Number
00h
Read/Write
1Bh
SMLT
Secondary Bus Master Latency
Timer
00h
Read/Write
1Ch
IOBASE
I/O Base Address Register
F0h
Read/Write
1Dh
IOLIMIT
I/O Limit Address Register
00h
Read/Write
1E-1Fh
SSTS
Secondary Status Register
02A0h
RO, Read/WriteC
20-21h
MBASE
Memory Base Address Register
FFF0h
Read/Write
22-23h
MLIMIT
Memory Limit Address Register
0000h
Read/Write
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