參數(shù)資料
型號： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 111/163頁
文件大小： 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
Datasheet
111
4.
Functional Description
This chapter describes the Graphics and Memory Controller Hub (GMCH2-M) interfaces, and boot
sequencing. The “System Address Map” provides a system-level address memory map and describes the
memory space controls provided by the GMCH2-M.
4.1.
System Memory and I/O Address Map
A mobile Intel
Pentium
III
processor or mobile Intel
Celeron
processor system based on the
GMCH2-M, supports 4 GB of addressable memory space and 64 KB+3 of addressable I/O space. (The
Pentium
III
bus I/O addressability is 64KB + 3). There is a programmable memory address (PAM)
space under the 1 MB region which can be controlled with programmable attributes of Write Only, or
Read Only. Attribute programming is described in the Configuration Register Description section. This
section focuses on how the memory space is partitioned and what these separate memory regions are
used for. The I/O address space is explained at the end of this section.
The mobile Intel
Pentium
III
processor, mobile Intel
Celeron
processor supports addressing of
memory ranges larger than 4 GB. The GMCH2-M Host Bridge claims any access over 4 GB by
terminating transaction (without forwarding it to the hub interface). Writes are terminated by dropping
the data and for reads the GMCH2-M returns all zeros on the host bus.
In the following sections, it is assumed that all of the compatibility memory ranges reside on the hub
interface. The exceptions to this rule are the VGA ranges, which may be mapped to the internal Graphics
Device.
The GMCH2-M Memory Map includes a number of programmable ranges, ALL of these ranges MUST
be unique and NON-OVERLAPPING. There are NO Hardware Interlocks to prevent problems in the
case of overlapping ranges. Accesses to overlapped ranges may produce indeterminate results.
4.1.1.
Memory Address Space
The following figure shows a high-level representation of the system memory address map. Figure 5
provides additional details on mapping specific memory regions as defined and supported by the
GMCH2-M chipset.
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