- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366260 > 82815EM Controller Miscellaneous - Datasheet Reference PDF資料下載
參數(shù)資料
| 型號： | 82815EM |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 124/163頁 |
| 文件大?。?/td> | 1049K |
| 代理商： | 82815EM |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁當前第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁
Intel
82815EM GMCH
R
124
Datasheet
4.7.4.
Legacy VGA Ranges
The legacy VGA memory range A_0000h-B_FFFFh is mapped either to the hub interface or to
AGP/PCI1 depending on the programming of the VGA Enable bit in the BCTRL configuration register
in GMCH2-M Device #1 configuration space, and the MDAP bit in the GMCH2-MCFG configuration
register in Device #0 configuration space. The same register controls mapping VGA I/O address ranges.
VGA I/O range is defined as addresses where A[9:0] are in the ranges 3B0h to 3BBh and 3C0h to 3DFh
(inclusive of ISA address aliases - A[15:10] are not decoded). The function and interaction of these two
bits is described below:
MDA Present (MDAP):
This bit works with the VGA Enable bit in the BCTRL register of device 1 to
control the routing of processor initiated transactions targeting MDA compatible I/O and memory
address ranges. This bit should not be set when the VGA Enable bit is not set. If the VGA enable bit is
set, then accesses to IO address range x3BCh-x3BFh are forwarded to the hub interface. If the VGA
enable bit is not set, then IO address range accesses x3BCh-x3BFh are treated like other IO accesses -
the cycles are forwarded to AGP if the address is within IOBASE and IOLIMIT and ISA enable bit is not
set, otherwise they are forwarded to the hub interface. MDA resources are defined as the following:
Memory: 0B0000h - 0B7FFFh
I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh,
Note:
Including ISA address aliases, A[15:10] are not used in decode.
Any I/O reference that includes the I/O locations listed above, or their aliases, will be forwarded to the
hub interface even if the reference includes I/O locations not listed above.
VGA Enable:
Controls the routing of processor initiated transactions targeting VGA compatible I/O
and memory address ranges. When this bit is set, GMCH2-M will forward the following processor
accesses to the AGP:
Memory accesses in the range 0A0000h to 0BFFFFh
I/O addresses where A[9:0] are in the ranges 3B0h to 3BBh and 3C0h to 3DFh
Note:
Inclusive of ISA address aliases - A[15:10] are not decoded.
When this bit is set, forwarding of these accesses issued by the processor is independent of the I/O
address and memory address ranges defined by the previously defined base and limit registers.
Forwarding of these accesses is also independent of the settings of the bit 2 (ISA Enable) of BCTRL if
this bit is “1”. If the VGA enable bit is set, then accesses to IO address range x3BCh-x3BFh are
forwarded to the hub interface. If the VGA enable bit is not set, then IO address range accesses x3BCh-
x3BFh are treated like other IO accesses - the cycles are forwarded to AGP if the address is within
IOBASE and IOLIMIT and ISA enable bit is not set, otherwise they are forwarded to the hub interface.
If this bit is “0” (default) , then VGA compatible memory and I/O range accesses are not forwarded to
AGP but rather they are mapped to the hub interface unless they are mapped to AGP via I/O and memory
range registers defined above (IOBASE, IOLIMIT, MBASE, MLIMIT, PMBASE, PMLIMIT
相關PDF資料 |
PDF描述 |
|---|---|
| 82820 | Interface IC |
| 82830009 | MOTOR 12VDC 2100RPM |
| 82830010 | MOTOR 24VDC 2100RPM |
| 82830MP | Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M) |
| 82840 | Interface IC |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 82-816-1000 | 功能描述:RF 連接器 ST Plug RG-108A 50 Ohm RoHS:否 制造商:Bomar Interconnect 產(chǎn)品:Connectors 射頻系列:BNC 型式:Jack (Female) 極性: 觸點電鍍:Gold 阻抗: 端接類型:Solder 主體類型:Straight Bulkhead 電纜類型: |
| 82-81641 | 制造商:CHOMERICS (PARKER) 功能描述: |
| 828168-1 | 制造商:TE Connectivity 功能描述:7P MT RV100 CONNECTOR |
| 828168-2 | 功能描述:7P MT TAND BU STECK RoHS:是 類別:連接器，互連式 >> 矩形 - 自由懸掛，面板安裝 系列:AMPMODU RV 100 RoHS指令信息:5-643816-8 Statement of Compliance 3D 型號:5-643816-8.pdf 標準包裝:500 系列:MTA-100 連接器類型:插座 觸點類型：:母形插口 位置數(shù):28 間距:0.100"（2.54mm） 行數(shù):1 行間距:- 安裝類型:自由懸掛 緊固型:鎖銷滑道 電纜端接:IDC 導線類型:離散式或帶狀纜線 線規(guī):28 AWG 特點:閉端，帶電極標記 觸點表面涂層:錫 觸點涂層厚度:80µin（2.03µm） 顏色:綠 包裝:散裝 相關產(chǎn)品:A1998-ND - HEAD ASSEM TOOL FOR MTA-100 RECP |
| 828169-1 | 功能描述:集管和線殼 2X7P MT TAND SOCKET CONNECTOR RoHS:否 產(chǎn)品種類:1.0MM Rectangular Connectors 產(chǎn)品類型:Headers - Pin Strip 系列:DF50 觸點類型:Pin (Male) 節(jié)距:1 mm 位置/觸點數(shù)量:16 排數(shù):1 安裝風格:SMD/SMT 安裝角:Right 端接類型:Solder 外殼材料:Liquid Crystal Polymer (LCP) 觸點材料:Brass 觸點電鍍:Gold 制造商:Hirose Connector |
發(fā)布緊急采購，3分鐘左右您將得到回復。