參數(shù)資料
型號: 82815EM
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù): 75/163頁
文件大?。?/td> 1049K
代理商: 82815EM
Intel
82815EM GMCH
R
Datasheet
75
3.6.33.
AMTT—AGP Multi-Transaction Timer (Device 0)
Address Offset:
BCh
Default Value:
00h
Access:
Read/Write
Size:
8 bits
AMTT is an 8-bit register that controls the amount of time that the GMCH2-M’s arbiter allows AGP/PCI
master to perform multiple back-to-back transactions. The GMCH2-M’s AMTT mechanism is used to
optimize the performance of the AGP master (using PCI semantics) that performs multiple back-to-back
transactions to fragmented memory ranges (and as a consequence it can not use long burst transfers).
The AMTT mechanism applies to the processor-AGP/PCI transactions as well and it guarantees to the
processor a fair share of the AGP/PCI interface bandwidth.
The number of clocks programmed in the AMTT represents the guaranteed time slice (measured in
66MHz clocks) allotted to the current agent (either AGP/PCI master or Host bridge) after which the AGP
arbiter will grant the bus to another agent. The default value of AMTT is 00h and disables this function.
The AMTT value can be programmed with 8 clock granularity. For example, if the AMTT is
programmed to 18h, then the selected value corresponds to the time period of 24 AGP (66-MHz) clocks.
(AGP mode only.)
7
3
2
0
Multi-Transaction Timer Count Value
Reserved
Bit
Description
7:3
Multi-Transaction Timer Count Value.
The number programmed in these bits represents the
guaranteed time slice (measured in eight 66MHz clock granularity) allotted to the current agent (either
AGP/PCI master or Host bridge) after which the AGP arbiter will grant the bus to another agent.
2:0
Reserved.
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