參數(shù)資料
型號(hào)： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁(yè)數(shù)： 45/163頁(yè)
文件大小： 1049K
代理商： 82815EM
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Intel
82815EM GMCH
R
Datasheet
45
3.6.4.
PCISTS—PCI Status Register (Device 0)
Address Offset:
06-07h
Default Value:
0090h
Access:
Read Only, Read/Write Clear
Size:
16 bits
PCISTS is a 16-bit status register that reports the occurrence of a PCI master abort and PCI target abort
on the PCI0 bus. PCISTS also indicates the DEVSEL# timing that has been set by the GMCH2-M
hardware for target responses on the PCI0 bus. Bits [15:12] and bit 8 are Read/Write clear and bits
[10:9] are read only.
15
14
13
12
11
10
9
8
0
SSE
RMAS
RTAS
(HW=0)
00
(HW=0)
7
6
5
4
3
0
(HW=1)
Reserved
(HW=1)
Reserved
Bit
Descriptions
15
Detected Parity Error (DPE)
. This bit is hardwired to a 0. Writes to this bit position have no affect.
14
Signaled System Error (SSE)
. This bit is set to 1 when GMCH2-M Device 0 generates an SERR
message over the hub interface for any enabled Device 0 error condition. Device 0 error conditions are
enabled in the PCICMD register. Device 0 error flags are read/reset from the PCISTS register. Software
sets SSE to 0 by writing a 1 to this bit.
13
Received Master Abort Status (RMAS)
. This bit is set when the GMCH2-M generates a hub
interface request that receives a Master Abort completion packet. Software clears this bit by writing a 1
to it.
12
Received Target Abort Status (RTAS)
. This bit is set when the GMCH2-M generates a hub interface
request that receives a Target Abort completion packet. Software clears this bit by writing a 1 to it.
11
Signaled Target Abort Status (STAS).
(Not implemented in GMCH2-M; is hardwired to a 0). Writes to
this bit position have no affect.
10:9
DEVSEL# Timing (DEVT)
. These bits are hardwired to 00. Writes to these bit positions have no affect.
Device 0 does not physically connect to PCI0. These bits are set to 00 (fast decode) so that optimum
DEVSEL timing for PCI0 is not limited by GMCH2-M.
8
Data Parity Detected (DPD).
This bit is hardwired to a 0. Writes to this bit position have no affect.
7
Fast Back-to-Back (FB2B).
This bit is hardwired to 1. Writes to these bit positions have no affect.
Device 0 does not physically connect to PCI. This bit is set to 1 (indicating fast back-to-back capability)
so that the optimum setting for PCI is not limited by GMCH2-M.
6:5
Reserved
.
4
Capability List (CLIST).
This bit is hardwired to ‘1’ to indicate that GMCH2-M always has a capability
list. The list of capabilities is accessed via register CAPPTR at configuration address offset 34h.
Register CAPPTR contains an offset pointing to the address of the first of a linked list of capability
registers. Writes to this bit position have no affect.
3:0
Reserved
.
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