Intel
82815EM GMCH
R
Datasheet
3
Contents
1.
Overview.................................................................................................................................... 12
1.1.
The Intel
815EM Chipset System ................................................................................ 13
1.2.
Intel
815EM Chipset GMCH2-M Overview.................................................................. 14
1.3.
Host Interface................................................................................................................ 15
1.4.
System Memory Interface ............................................................................................. 16
1.5.
Multiplexed AGP and Display Cache Interface.............................................................. 16
1.6.
AGP Interface................................................................................................................ 16
1.6.1.
Display Cache Interface.............................................................................. 17
1.7.
Hub Interface................................................................................................................. 17
1.8.
GMCH2-M Integrated Graphics (GFX) Support............................................................ 17
1.8.1.
Intel Dynamic Video Memory Technology (D.V.M.T.) ............................... 18
1.8.2.
Display......................................................................................................... 18
1.8.3.
Digital Video Out Port (DVO)....................................................................... 18
1.9.
System Clocking............................................................................................................ 18
1.10.
GMCH2-M Power Delivery............................................................................................ 18
1.11.
References.................................................................................................................... 18
2.
Signal Description...................................................................................................................... 19
2.1.
Host Interface Signals ................................................................................................... 20
2.2.
System Memory Interface Signals................................................................................. 22
2.3.
AGP Interface Signals................................................................................................... 22
2.3.1.
AGP Addressing Signals............................................................................. 23
2.3.2.
AGP Flow Control Signals........................................................................... 24
2.3.3.
AGP Status Signals..................................................................................... 24
2.3.4.
AGP Clocking Signals - Strobes.................................................................. 25
2.3.5.
AGP FRAME# Signals ................................................................................ 26
2.3.6.
AGP C3 support Signals ............................................................................. 28
2.4.
Display Cache Interface Signals.................................................................................... 29
2.5.
Hub Interface Signals.................................................................................................... 30
2.6.
Display Interface Signals............................................................................................... 30
2.7.
Digital Video Output Signals/TV-Out Pins..................................................................... 31
2.8.
Power Signals................................................................................................................ 32
2.9.
Clock Signals................................................................................................................. 32
2.10.
Miscellaneous Interface Signals.................................................................................... 33
2.11.
GMCH2-M Power-Up/Reset Strap Options................................................................... 33
2.12.
Multiplexed Display Cache and AGP Signal Mapping................................................... 34
3.
PCI Configuration Registers....................................................................................................... 35
3.1.
Register Nomenclature and Access Attributes.............................................................. 35
3.2.
GMCH2-M Register Introduction................................................................................... 36
3.3.
I/O Mapped Registers ................................................................................................... 36
3.3.1.
CONFIG_ADDRESS
Configuration Address Register............................. 37
3.3.2.
CONFIG_DATA
Configuration Data Register........................................... 38
3.4.
PCI Bus Configuration Mechanism ............................................................................... 39
3.5.
PCI Configuration Space Access.................................................................................. 39