參數(shù)資料
型號: 82815EM
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù): 16/163頁
文件大小: 1049K
代理商: 82815EM
Intel
82815EM GMCH
R
16
Datasheet
1.4.
System Memory Interface
The Intel
815EM chipset GMCH2-M integrates a system memory controller that supports a 64-bit, 100-
MHz SDRAM array. The only DRAM type supported is industry standard Synchronous DRAM
(SDRAM). The SDRAM controller interface is fully configurable through a set of control registers.
Complete descriptions of these registers will be available in a future revision of this document.
The GMCH2-M supports industry standard 64-bit wide DIMMs for desktop platforms and SO-DIMMs
for mobile platforms with SDRAM devices. The twelve multiplexed address lines, SMAA[12:0], along
with the two bank select lines, SBS[1:0], allow the GMCH2-M to support 2M, 4M, 8M, and 16M x64
DIMMs. Only asymmetric addressing is supported. The GMCH2-M has 12 SCS# lines enabling the
support of up to six 64-bit rows of SDRAM. The GMCH2-M targets SDRAM with CL2 and CL3 and
supports both single and double-sided DIMMs for desktop and SO-DIMMs for mobile platforms.
Additionally, the GMCH2-M also provides a seven deep refresh queue. The GMCH2-M can be
configured to keep multiple pages open within the memory array. Pages can be kept open in any one
bank of memory.
SCKE[5:0] is used in configurations requiring powerdown mode for the SDRAM. Each SCKE can be
dynamically powerdown if not in use. This scheme will save significant amount of power since only one
SO-DIMM at any given time will be functional and all the rest will be powered down.
1.5.
Multiplexed AGP and Display Cache Interface
The Intel
815EM chipset GMCH2-M multiplexes a display cache interface for internal graphics 3D
performance improvement with an AGP controller interface. The Display Cache is used only in the
internal graphics. When an AGP card is populated in the system, the Intel
815EM chipset GMCH2-M
internal graphics will be disabled and the AGP controller enabled.
1.6.
AGP Interface
A single AGP port is supported by the GMCH2-M AGP interface. The AGP buffers operate in one of
two selectable modes:
3.3V drive,
not
5 volt safe - This mode is compliant to the AGP 1.0 and 2.0 specs.
1.5V drive,
not
3.3 volt safe - This mode is compliant with the AGP 2.0 spec.
The following table shows the AGP Data Rate and the Signaling Levels supported by the GMCH2-M:
Table 1. AGP Data Rate and Signaling Levels
Signaling Level
Data Rate
1.5v
3.3v
1x AGP
Yes
Yes
2x AGP
Yes
Yes
4x AGP
Yes
No
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