Intel
82815EM GMCH
R
Datasheet
7
4.12.13.
System Reset for the GMCH2-M................................................................................. 145
System Clock Description ........................................................................................... 146
4.14.1.
External Clock Sources............................................................................. 146
4.14.2.
Internal Clock Sources.............................................................................. 146
Power Management .................................................................................................... 146
4.15.1.
Specifications Supported........................................................................... 147
General Description of ACPI Power States................................................................. 147
Power State Transition Rules at Platform Level.......................................................... 148
ACPI Support............................................................................................................... 149
4.18.1.
Full on (C0 State)...................................................................................... 149
4.18.2.
Stop Grant or Quick Start (C2 State) ........................................................ 149
4.18.3.
Stop Clock (C3 State)................................................................................ 149
4.18.4.
C3 Support AGP Port Signal..................................................................... 150
4.18.5.
Power-on-suspend (POS) (S1 State)........................................................ 150
4.18.6.
Suspend-to-RAM (STR) (S3 State)........................................................... 151
4.18.7.
Suspend to DISK (STD) S4 State ............................................................. 151
4.18.8.
Graphics Controller Requirements............................................................ 151
4.18.8.1.
The D0 State ................................................................................ 151
4.18.8.2.
The D3 State ................................................................................ 151
DDC (Display Data Channel) .................................................................... 145
4.13.
4.14.
4.15.
4.16.
4.17.
4.18.
5.
Pinout and Package Information.............................................................................................. 153
5.1.
GMCH2-M Pinout........................................................................................................ 153
5.2.
GMCH2-M Package Dimensions ................................................................................ 160
6.
Testability................................................................................................................................. 162
6.1.
XOR Chain .................................................................................................................. 163
6.2.
All Z ............................................................................................................................. 163