參數(shù)資料
型號: 82815EM
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù): 118/163頁
文件大?。?/td> 1049K
代理商: 82815EM
Intel
82815EM GMCH
R
118
Datasheet
4.3.2.1.
APIC Configuration Space (FEC0_0000h -FECF_FFFFh, FEE0_0000h-
FEEF_FFFFh)
These ranges are reserved for APIC configuration space. The default Local APIC configuration space is
FEE0_0000h to FEEF_FFFFh.
Processor accesses to the Local APIC configuration space do not result in external bus activity since the
Local APIC configuration space is internal to the processor. However, a MTRR must be programmed to
make the Local APIC range uncacheable (UC). The Local APIC base address in each processor should
be relocated to the FEC0_0000h (4GB-20MB) to FECF_FFFFh range so that one MTRR can be
programmed to 64 KB for the Local and I/O APICs.
The I/O APIC(s) usually reside in the I/O Bridge
portion (ICH2-M) of the chip-set or as a stand-alone component(s).
I/O APIC units will be located beginning at the default address FEC0_0000h. The first I/O APIC will be
located at FEC0_0000h. Each I/O APIC unit is located at FEC0_x000h where
x
is I/O APIC unit number
0 through F(hex). This address range will be normally mapped via the hub interface to PCI.
Note:
There is no provision to support an I/O APIC device on AGP.
The address range between the APIC configuration space and the High BIOS (FED0_0000h to
FFDF_FFFFh) is always mapped via the hub interface to PCI.
4.3.2.2.
High BIOS Area (FFE0_0000h -FFFF_FFFFh)
The top 2 MB of the Extended Memory Region is reserved for System BIOS (High BIOS), extended
BIOS for PCI devices, and the A20 alias of the system BIOS. Processor begins execution from the High
BIOS after reset. This region is mapped via the hub interface to PCI so that the upper subset of this
region aliases to 16 MB-256 MB range
.
The actual address space required for the BIOS is less than 2
MB but the minimum processor MTRR range for this region is 2 MB so that full 2 MB must be
considered. The ICH2-M supports a maximum of 1MB in the High BIOS range.
4.4.
System Management Mode (SMM) Memory Range
The GMCH2-M supports the use of main memory as System Management RAM (SMRAM) enabling the
use of System Management Mode (SMM). The GMCH2-M supports three SMM options:
Compatible SMRAM (AB segment enabled)
High Segment (HSEG)
Top of Memory Segment (TSEG)
System Management RAM (SMRAM) space provides a memory area that is available for the SMI
handler's and code and data storage. This memory resource is normally hidden from the operating
system so that the processor has immediate access to this memory space upon entry to SMM. The
GMCH2-M provides three SMRAM options:
Below 1 MB option that supports compatible SMI handlers.
Above 1 MB option that allows new SMI handlers to execute with write-back cacheable SMRAM.
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