參數(shù)資料
型號： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 86/163頁
文件大?。?/td> 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
86
Datasheet
3.7.13.
SMLT—Secondary Master Latency Timer Register (Device 1)
Address Offset:
1Bh
Default Value:
00h
Access:
Read/Write
Size:
8 bits
This register controls the bus tenure of the GMCH2-M on AGP/PCI. SMLT is an 8-bit register that
controls the amount of time the GMCH2-M as an AGP/PCI bus master, can burst data on the AGP/PCI
Bus. The Count Value is an 8 bit quantity, however SMLT[2:0] are reserved and assumed to be 0 when
determining the Count Value. The GMCH2-M’s SMLT is used to guarantee to the AGP master a
minimum amount of the system resources. When the GMCH2-M begins the first PCI bus cycle after
being granted the bus, the counter is loaded and enabled to count from the assertion of FRAME#. If the
count expires while the GMCH2-M’s grant is removed (due to AGP master request), then the GMCH2-
M will lose the use of the bus, and the AGP master agent may be granted the bus. If GMCH2-M’s bus
grant is not removed, the GMCH2-M will continue to own the AGP/PCI bus regardless of the SMLT
expiration or idle condition. Note that the GMCH2-M must always properly terminate an AGP/PCI
transaction with FRAME# negation prior to the final data transfer.
The number of clocks programmed in the SMLT represents the guaranteed time slice (measured in
66Mhz PCI clocks) allotted to the GMCH2-M, after which it must complete the current data transfer
phase and then surrender the bus as soon as its bus grant is removed. For example, if the SMLT is
programmed to 18h, then the value is 24 AGP clocks. The default value of SMLT is 00h and disables
this function. When the SMLT is disabled, the burst time for the GMCH2-M is unlimited (i.e. the
GMCH2-M can burst forever).
7
3
2
0
Secondary MLT Counter Value
Reserved
Bit
Description
7:3
Secondary MLT Counter Value.
Default=0 i.e. SMLT disabled
2:0
Reserved.
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